Athens, Greece -- Mar. 9, 2015 -- Alma Technologies S.A., a semiconductor IP provider, today announced the immediate availability of a new very high performance JPEG Encoder IP Core, initiating a new product line of scalable parallel processing Ultra High Throughput Image and Video Compression IPs. This new UHT™ series of IP is designed to enable the massive pixel rates of 4K/8K resolutions and high frame rate video applications in highly cost-effective FPGA and ASIC technologies.
Powered by multiple internal processing engines, the new UHT-JPEG-E Baseline and Extended JPEG Encoder brings all the speed needed today with its scalable parallel architecture. Each input image or video frame is split internally into chunks that get assigned to the internal compression units. This is done in a way which is totally transparent to the system utilizing the IP, abstracting all the parallelization complexity from the rest SoC components.
The UHT™ JPEG encoder is strictly compliant to the ITU T.81 and ISO/IEC 10918-1 specifications. It supports 4:4:4, 4:2:2, 4:2:0 and 4:0:0 chroma sampling formats, in 8, 10 or 12 bits per component sample depth. The core uses a single uncompressed data input interface - accepting raster scan pixels - and produces a single, ready-to-use and fully compliant JPEG stream output. The UHT-JPEG-E employs also a constant bitrate video encoding option, supporting the bandwidth or storage constrained motion JPEG applications. Its operation is completely standalone, without needing any host processing power. The encoder can be implemented using only on-chip memory resources, while using off-chip memory too is also natively supported.
Packed with configurable expanded features and designed for silicon speed versus size versatility, the UHT™ architecture offers uncompromised image quality and ultra high performance in the most efficient way. The number of internal compression units is configurable, adapting to the implementation technology speed, and non-critical resources are shared between the multiple compression engines. Encoding rates up to 32 MSamples/MHz are possible by the scalable UHT-JPEG-E architecture, enabling ultra high throughput even in low-cost FPGA devices.
For example, 2160p30 4:2:2 8-bit (500 MSamples/s) video can be encoded in an Altera Cyclone V device using 30K LEs, or in a Xilinx Artix-7 device using 40K LCs. These figures correspond to the slowest device speed grade. Increasing the number of internal compression units, the performance in the same FPGA device families can scale up to over 2 GSamples/s. In the TSMC 40nm LP process, a 3 GSamples/s throughput configuration uses 300K gates - excluding memories area - and scaling to more than 20 GSamples/s is possible.
The matching UHT™ JPEG decoder will be released next month, followed by UHT™ H.264 and JPEG 2000 encoding IPs which are expected in the next two quarters.
Alma Technologies IPs are designed to ensure a fast and trouble-free integration in any FPGA or ASIC design. They are available either as standalone, high quality and implementation technology independent VHDL or Verilog RTL, or as optimized Netlists for Altera, Lattice, Microsemi and Xilinx FPGA and SoC devices.
About Alma Technologies
Alma Technologies is a semiconductor IP provider, developing high quality IP cores since 2001. Its products stand out for their engineering, being complete, easy-to-use and reliable IP solutions. Best-in-class technical support and a long track record of proven designs by more than 200 licensees provide Alma Technologies customers with the best service and value. Learn more at: www.alma-technologies.com