Synopsys convolutional neural network coprocessor lowers power for vision processing.
by Bernard Cole, EETimes, Mar. 30, 2015 –
FLAGSTAFF, Ariz. - The growth in embedded vision systems - systems that extract meaning from visual inputs - is driving demand for more performance- and power-efficient vision-processing capabilities. Many companies have risen to respond to this demand: AMD, CEVA, Imagination, Intel, Nvidia, and various Arm licensees. They use a variety of hardware: FPGAs, FPGA/MPU combinations, graphics processing units, and specialized heterogeneous multicore designs optimized for the task.
Now Synopsys Inc. (Mountain View, CA) has released its alternative solution, the DesignWare EV processor core family (shown below), designed to be integrated into an SoC with any of a number of host CPUs, including those from Arm, Intel, Imagination MIPS, PowerPC and others. It currently includes two members, the EV52 and EV54, optimized for vision computing applications. Fabricated using a 28-nanometer process, the EV52 features a dual-core RISC processor based on the company's ARC instruction set, operating at up to 1GHz. The EV54 features a quad-core implementation offering higher performance than the EV52. Both incorporate anywhere from two to eight programmer configurable object detection engine processing elements (PEs).