The 6th generation TCP Core Accelerates an unprecedented number of 16K TCP & UDP Sessions in 77 nanoseconds with 97% TCP throughput, providing 8x – 50x advantage over the legacy Software TCP stack.
Milpitas, CA., Mar. 31st, 2015— Intilop, Inc. a pioneer, most respected and recognized leader in providing Ultra-Low latency and Hyper Performance Complex Networking Protocol Accelerators, Mega IP Cores, Systems and Solutions since 2009, delivers their Enhanced 10G bit 16K concurrent-TCP-session Hardware Accelerator Pre-Ported and tested on Altera and Xilinx FPGAs. This subsystem with 10G TCP Accelerator (TCP Full Offload Engines) that implements16 Thousand Simultaneous TCP Connections, unlimited continuous connections and Bandwidth of more than 1.1 Gigabyte/sec per port regardless of number of simultaneous or active TCP Sessions. In addition, it delivers the same hyper performance with same Ultra-low latency and Zero Jitter irrespective of number of active connections from 1 - 16384. A demo showing Thousands of TCP Servers and TCP Clients Sending and receiving TCP connection traffic is available upon request. An earlier version of this was demoed in SC14 in New Orleans, LA, November 17 – 20, 2014.
This deployment-ready, pre-verified solution provides networking OEMs an Ultra-low-latency and Hyper-performance for all networking equipment segments that have to process TCP Protocol. Available in Altera/Quartus 14.x and Xilinx/Vivad2014.x. Now clients can accomplish this at line rate which is orders of magnitude faster than processing in TCP software stack, irrespective of whether the stack is running on host CPU or a CPU on a plugged in NIC. Specifically, these TCP & UDP Accelerator are targeted towards the next generation of Cloud Computing, Data Center, Network Security, Telecomm and all other Hyper Performance Network Computing server appliances in government and private enterprise system applications. The FPGA platform offers an ‘Out of the box’ working TCP hardware stacks with unprecedented functionality, ultra small core size, high performance and flexibility. The Full TCP core runs without any CPU involvement through all stages of TCP transactions, including connection set up, data transfer, tcp-retries and connection tear down. The TCP connections maintain the same high throughput and low latency/processing times regardless of number of simultaneous connections in progress. It also implements Full ARP protocol hardware which makes a truly full TCP accelerator that runs without any involvement from the host or local CPU/software. This is a vast difference compared with other leading TCP Accelerator ASICs on various NICs that implement partial TCP Offloads and suffer major performance degradation when handling just 10-20 simultaneous TCP Sessions, not to speak of hundreds or thousands of simultaneous TCP connections. The unprecedented TCP throughput of more than 95% for large and small size payload data transfers on a 10G network, which is 8 – 50 x higher as compared to TCP /IP software running on typical host CPU which is the de-facto standard.
In addition, the whole SOC subsystem containing EMAC & TOE & UOE which only takes up less than 18K Slices/40K LUTs and 2MB BRAM, It also integrates a DDR3 interface. This enhanced version automatically stores received and transmit payloads to DDR in the event internal BRAMs are filled up. Clients will be able to utilize FPGAs technology from Xilinx and Altera to get all of the benefits of TCP hardware acceleration. A complete FPGA board/development Kit is delivered with pretested TOE & EMAC and PHY subsystem which allows customers to start using the TOE core right out of the box. A ‘Super simple’ FIFO based User interface allows customers to also integrate their value add logic in a very short time. It is expected to hasten the adaption of this technology in the vast array of next generation network connected devices.
Their previous 5 generations of Full TCP Accelerators provide up to 256 Simultaneous TCP Connections and have also been available on most FPGA boards/platforms.
As a pioneer, Intilop was the first company to deliver a series of Full TCP Offload Engines on FPGAs in 2009. Their sub 100 ns latency MAC+TOE&UOE are considered a ‘Gold Standard’ by the industry experts.
The latency barrier of 100 nanoseconds and throughput of more than 1 G byte/s per port had been set by them since their first 10G Series of TCP engines in 2011. And, now the same performance metrics are provided across all 16 Thousand Simultaneous TCP Sessions.
The highly deterministic performance, reliable and proven ultra-low latency, coupled with customizability offered by the 10G TOE is being effectively applied to gain wire-speed competitive edge by all Networking Equipment makers.
Customers now have a larger variety of cutting edge TCP offload products from Intilop to choose from, when they want to move up in the nanosecond league from the microsecond league. By utilizing the full benefits of pivotal 10G TOE technologies they can confidently exceed their challenging network performance objectives.
The TOE’s Patent pending architecture is highly scalable, customizable and adaptable without compromising the low latency and performance. Intilop’s product-line solutions are available in flexible FPGA/ASIC/SoC technologies which can easily accommodate diverse set of Networking System Design specifications.
The Series of Cores implementing 16K, 8K, 1K, 256 and 32 Concurrent TCP Sessions is available at-
Intilop is a developer, provider, a recognized leader and pioneer in advanced networking silicon IP and system solutions, custom hardware solutions, SoC/ASIC/FPGA integrator and total system solutions provider for Networking, Network Security, storage and Embedded Systems.