New Cycle-Accurate TeakLite® Model is Integrated into AXYS® Design's MaxSim™ Multicore Simulation Environment and the Mentor Graphics® Seamless® Co-Verification Tool
SANTA CLARA and PALO ALTO, California; August 8, 2002 - DSP Group, Inc. (NASDAQ: DSPG), the world leader in the development and licensing of Digital Signal Processor (DSP) cores and AXYS Design Automation, Inc. announced today the immediate availability of the fast cycle-accurate model for the popular TeakLite DSP core from DSP Group. The simulation model was developed using AXYS Design's MaxCoreâ tool and the processor description in C-based Language for Instruction Set Architectures (LISA). The MaxCore model delivers over one million cycles per second on a 1GHz Pentium host and supports scalable multicore simulation and debugging. DSP Group's thorough set of hardware test vectors has been applied to verify the functional match between the simulation model and its register transfer level (RTL) reference on a cycle by cycle basis.
Many electronic communication and consumer devices being created for the current market require Digital Signal Processing capabilities using limited power supplies and fast processing times to enable these devices to function efficiently. The TeakLite core is a 16-bit general-purpose DSP core targeted for applications requiring low power consumption, low bandwidth and high processing volume such as 2G and 2.5G wireless communication, as well as Internet audio formats, including MP3 and WMA, and Voice-over-IP phones. The new model of the TeakLite DSP core is part of the extensive MaxLibâ library of processor models for AXYS Design's MaxSimä Developer Suite. With MaxSim, users can create complete, application-specific platform models with multiple cores as virtual prototypes for early architecture exploration, pre-silicon embedded software development and multicore debugging. Early pre-silicon verification of hardware and software reduces the need for costly silicon re-spins and accelerates the product development cycle; thereby shortening the overall time-to-market. In addition to DSP Group's SmartCores™, the MaxLib library contains a rich set of models for other popular processor cores and System-on-a-Chip (SoC) components from ARM, MIPS and others.
"Our ongoing collaboration with AXYS Design in the system design methodology space is part of a strong commitment to our licensees, enabling them to achieve successful product releases of complex designs in the shortest possible timeframe." said Eyal Ben-Avraham, VP of Support and Applications at DSP Group's Ceva Licensing Division. "The newly-released high performance model is instrumental for efficient architectural trade-off analysis of multicore platforms, early development of embedded DSP software and simultaneous verification of hardware and software for designs incorporating our DSP core."
"The speed of the cycle-accurate and pipeline-accurate TeakLite simulation model, and the flexibility of our MaxSim multicore modeling solution, enable hardware-aware software development and trade-off analysis without compromising accuracy, at the earliest possible time," said Frank Schirrmeister, VP of Business Development, AXYS Design. "This level of accuracy is especially crucial for multi-core platform architectures incorporating the TeakLite DSP in which pipeline effects can significantly influence the performance of time-critical DSP applications."
AXYS Design also offers the cycle-accurate TeakLite model as part of the co-verification models available for the Mentor Graphics Seamless hardware/software co-verification environment. The new Seamless TeakLite Processor Support Package (PSP) will be available through the sales and marketing channels of Mentor Graphics.
At the ARM Partner Meeting, APM, (August 14-15, Cambridge, UK), AXYS Design and DSP Group will be demonstrating the dual-core MaxSim platform including DSP Group's TeakLite DSP processor and the ARM926EJ-S JAVA-enabled processor from ARM. Please visit AXYS Design at the APM (booth #112).
About AXYS Design Automation, Inc.
AXYS® Design Automation, Inc. is a provider of fast, accurate, and integrated processor and SoC (System-on-a-Chip) C/C++ modeling and simulation solutions for the development of high software content SoC devices. The use of AXYS Design's tool suites in the pre?silicon phase substantially shortens the SoC design cycle by enabling early system integration and embedded software development, thus reducing NRE cost and time to market.
The MaxSim™ Developer Suite is a tool enabling the modeling and verification of multi-core SoC designs. The MaxCore™ Developer Suite is a toolset for the automatic generation of processor models and software development tools. MaxLib™ is AXYS Design's growing library of models for popular SoC components. For more information, visit the AXYS Design web site at http://www.axysdesign.com .
About DSP Group, Inc.
DSP Group, Inc., is a global leader in the development and marketing of high-performance, cost-effective, licensable digital signal processing (DSP) cores. The company's family of DSP cores provides ideal solutions for low-power, cost-effective applications, such as cellular, broadband communications, VoIP, multimedia, advanced telecommunications systems, disk-drive controllers, and other types of embedded-control applications. By combining its DSP core technologies with its proprietary, advanced speech-processing algorithms, DSP Group also delivers a wide range of enabling, application-specific integrated circuits (ICs) for full-featured, integrated-telephony products and applications, including spread spectrum wireless technologies. DSP Group maintains an international presence with offices located around the globe. More information about DSP Group is available from its Web site at http://www.dspg.com /.
AXYS, MaxCore and MaxLib are registered trademarks of AXYS Design Automation, Inc. MaxSim is a trademark of AXYS Design Automation, Inc.
PalmDSPCore, Teak, TeakLite and OakDSPCore are registered trademarks and SmartCores is a trademark of DSP Group, Inc.
Other brands and products referenced herein are the trademarks or registered trademarks of their respective holders.