New technology allows use of assertions throughout the entire design flow, and accelerates assertion based verification by 1000x or more
Sunnyvale, CA - August 19, 2002 - Axis Systems, Inc. today announced Assertion Processor, a new system-on-chip verification technology that for the first time enables designers to accelerate and emulate assertions, which are used to verify chips. Assertion Processor accelerates assertion-based verification by 1000 times or more, and is expected to increase designers' confidence that design flaws will be found before a chip is manufactured.
"As today's chip designs move toward multiple millions of gates, engineers require new tools and methodologies to verify these designs," said Mike Tsai, president and CEO of Axis. "By combining assertions with our general-purpose ReConfigurable Computing verification platform, we're giving our customers the performance, productivity, and debugging tools they need to meet verification requirements for the next generation of designs."
Assertion Processor will enable designers to incorporate assertions into their designs during acceleration and emulation, without requiring any changes to their existing verification methodology. Axis' entire product line has incorporated the new Assertion Processor, including Xtreme®, Xtreme II™, and Xcite®. All of the Axis products are based on the company's patented ReConfigurable Computing (RCC) technology, which combines simulation, acceleration, and emulation on a single platform.
Assertions are statements that document a designer's assumptions and properties of the design. A powerful tool used to crosscheck a design's actual versus intended behavior, assertions enable system designers to formally specify intended behavior so that verification engineers can ensure that an electronic system is acting according to specification.
According to Jason Andrews, product manager at Axis Systems, Axis is committed to promoting the use of assertions, and maintains a neutral position on specific assertion methods. "We want to help educate engineers on how to incorporate assertions into their design flow, and provide the technology to leverage these assertions in the simulation and emulation of today's complex designs," said Andrews.
Currently four approaches to assertions exist:
- Declarative assertions using a library of Verilog monitor modules
- Procedural statements using a Verilog assert construct
- Formal property languages
- Pseudo-comment directives
The most common use of assertions today are the declarative assertions in the Open Verification Library (OVL), a free assertion monitor library of Verilog modules that can be easily instantiated into a design (see www.verificationlib.org ).
"Axis is enabling OVL to be used during all phases of the design cycle," said Mark Curry, senior design engineer of Texas Instruments DSL Business Unit, an Axis customer. "We see an advantage in not having to remove assertions or run them in software simulation when we're ready to move into simulation acceleration. With Axis and OVL, we can get the observability we need to debug our design, and the performance we need to remain productive."
At times, designers want to specify assertions using procedural statements. This is the case with the new 'assert' construct, which is part of the SystemVerilog 3.0 specification approved by Accellera, an industry organization focused on language-based electronic design standards. Axis has joined Accellera, currently holds a seat on the board of directors, and is involved in technical committees related to OVL and SystemVerilog assertions.
"Assertions are an important part of an effective verification methodology," said Dennis Brophy, Accellera Chairman. "Axis technology and support for Accellera's OVL assertions today and System Verilog assertions in the future will go a long way to help designers adopt assertions without compromising their emulation methodology or performance."
A methodology that enables assertion-based verification within a dynamic simulation and formal verification environment is Synopsys' OpenVera™ Assertions. Axis has been working with Synopsys to provide support for the acceleration of OpenVera Assertions.
"OpenVera Assertions is an open language designed to enable a full verification flow, including simulation, coverage, testbench, formal, and hardware acceleration," said Rich Goldman, vice president of Strategic Market Development at Synopsys, Inc. "Momentum for OVA continues to build. Designers are already using an assertion-based verification methodology with OVA, and Axis' support will enable them to take advantage of this methodology in the acceleration and emulation environment."
Another approach that has been taken to specify assertions is the use of pseudo-comments. By embedding assertions in comments, they can be put directly into the RTL code and will not interfere with the Verilog syntax or require any changes to the simulator. Axis partner 0-In Design Automation is working in this area. ( See today's related news release on the joint 0-In/Axis assertion solution .)
Assertion Processor Technology Background
Assertions have two parts: detection and failure processing. Assertion Processor accelerates detection by running assertion checking in RCC at hardware speed. Similar to a microprocessor interrupt, Assertion Processor receives interrupts when assertions fail and activates a software service routine that runs on the workstation and has access to behavioral code such as $display or PLI.
"Assertions are an ideal application for Axis' acceleration and emulation systems," added Jason Andrews. "Because our RCC engine is event driven, it can easily handle interrupts and return immediate feedback to a designer when a failure is detected."
Assertion Processor enables engineers to maintain the use of assertions from simulation to acceleration and into emulation without being forced to execute assertion detection in software simulation or remove assertions before emulation.
With Assertion Processor, assertion detection executes in parallel with the design running in Axis' ReConfigurable Computing engine, so designers can enjoy the same simulation speed up of 1000x or more that Axis' Xcite and Xtreme verification systems offer. By accelerating both the design and the assertion detection, users get the highest level of simulation performance while maintaining the increased observability provided by assertions.
Users achieve the highest debugging productivity by combining Assertion Processor with VCD-on-Demand (VoD) to generate waveform information. Assertions pin-point design errors and VoD provides the most efficient way to produce waveforms starting at the point of assertion failure and working back to the root cause of the problem without having to rerun simulation.
Pricing and Availability
Assertion Processor technology is available now, and is currently being used by Axis and its partners to provide integrated assertion solutions for Axis' Xtreme and Xtreme II verification systems. It is also available as an upgrade to Xcite customers.
About Axis Systems
Axis Systems, Inc. offers high-performance verification platforms for the hardware and software development of complex electronic system and system-on-a-chip designs. Axis' products help increase confidence in new designs, improve overall verification productivity and shorten time to market. On a single platform and with one design database, Axis' patented ReConfigurable Computing (RCC) technology provides software simulation, accelerated simulation, system emulation and hardware/software co-verification. Customers include the world's leading networking and multimedia companies. Axis is headquartered at 209 Java Drive, Sunnyvale, CA 94089. To learn more about Axis, visit www.axiscorp.com .
OpenVera is a trademark of Synopsys, Inc. Other marks are the property of their respective owners.