The high throughput 40G TCP Endpoint delivers an ultra-low-latency of 96.0 nanoseconds
Santa Clara, California, June 11, 2015 - Algo-Logic Systems, a recognized leader in providing hardware-accelerated, deterministic, ultra-low-latency products, systems and solutions for accelerated finance, datacenter acceleration, and embedded system industries, today announced availability of their new 5th Generation 40G TCP Endpoint. The IP-Core enables FPGA-implemented logic to directly communicate over 40 Gigabit Ethernet networks with remote hardware or software devices and includes easy to use hardware application programming interface that supports multiple real-world accelerated datacenter use cases.
The reliable and network-tested 40G TCP Endpoint delivers ultra-low-latency of 96.0 nanoseconds at full duplex rates of 80 Gbps. This 40G TCP Endpoint IP-Core solution runs on the Altera Stratix V FPGA on platforms with QSFP+ ports. Supported platforms include Altera’s 100G development board, PLDA Xpress GX5-LP, and Bittware S5-PCIe-HQ; additional platforms will be supported soon. The TCP Endpoint can also be used as an endpoint for traffic from the new 25 Gbps Ethernet standard on select boards with faster SFP28 SERDES.
Each instance of the core supports up to 512 sessions of TCP traffic. However, unlike a software TCP endpoint, Algo-Logic’s FPGA TCP Endpoint enables a single session to send traffic at rates up to 40 Gbps in datacenters where round-trip latency is low. Additionally, it supports aggregate traffic flows that add to 40 Gbps for multiple sessions running over higher latency networks. The TCP Offload Engine (TOE) configurations are specifically designed for real-world datacenter acceleration and commercial deployment scenarios. The key features of the 40G TCP Endpoint include:
- Allows scaling from a single TCP session running at 40 Gbps up to 512 sessions per 40G port
- Permits each session to use a unique MAC, Port, and IP Addresses
- Utilizes a small logic footprint of under 5.0% ALMs in a Stratix V A7 FPGA
- Operates at full 40GE line rate (80 Gbps duplex) on platforms with QSFP+ links
- Operates at full 25GE line rate (50 Gbps duplex) on FPGA platforms with SFP28 links
- Provides very high throughput with small and large payloads including jumbo frames
- Delivers reliable delivery of data directly between FPGA accelerators and host machines
- Runs independently of the Operating System (OS) without software interaction
- Includes a standard API for control and configuration
- Instantiates to support up to 960 Gbps on a Stratix V A7 using 12 QSFP+ duplex ports
Algo-Logic’s 40G TCP Endpoint can be seamlessly integrated with other components of Algo-Logic’s Gateware Defined Networking® (GDN) IP-Core libraries, such as the Key Value Store (KVS) in-memory database, as well as with customer applications that perform N-Tuple packet classification and Network Functional Virtualization (NFV).
“FPGAs are increasingly deployed in datacenters for data streaming applications which require lower latency and CPU offload. Algo-Logic is providing a strong solution to meet those needs for high throughput 40G TCP networking traffic,” said Mike Strickland, director of Altera’s computer and storage systems business unit.
“We are pleased to launch our industry-first 40 Gbps TCP Endpoint for network traffic acceleration,” said John Lockwood, CEO of Algo-Logic Systems, Inc., “it enables logic in datacenter accelerators to transfer massive volumes of data with the lowest possible latency and power.”
Algo-Logic's world-class hardware-accelerated systems and solutions are used by datacenter operators to increase throughput, minimize latency, and reduce both capital and operating expenses.
Price and availability
For additional information, please contact Info@algo-logic.com or visit Algo-Logic’s website at: http://www.algo-logic.com
About Algo-Logic Systems
Algo-Logic Systems, Inc., is a recognized leader and developer of fast time-to-market gateware libraries for Field Programmable Gate Array (FPGA) devices. Algo-Logic IP-Cores are used to lower latency in trading systems, increase packet throughput in datacenters, and lower power for data processing in embedded systems.