Athens, Greece, Jun. 22, 2015 -- Alma Technologies S.A., a semiconductor IP provider, today announced the immediate availability of a new Ultra High Throughput JPEG decoder IP Core, completing its UHT™ JPEG compression family of IPs. This new UHT JPEG decoder IP, paired with Alma Technologies UHT JPEG encoder, offers massive pixel rates with very low end-to-end latency in video transmission systems using constrained bandwidth channels. The low complexity of this solution enables 4K/8K resolutions and high frame rates using highly cost-effective FPGA or ASIC technologies.
The key advantage of using JPEG compression is the simplicity of the resulting implementation, which keeps system costs to a minimum even when multiple parallel processing engines are used to speed-up processing. JPEG is capable of visually lossless compression in low compression ratios, while retaining a very good image quality up to medium compression ratios. In addition, the Constant Bitrate feature of the Alma Technologies UHT JPEG encoder, permits minimal memory buffering in the decoder side, enabling sub-frame latency in a live video system with compression, transmission and decompression. Applications such as video surveillance, operating remote machinery over video feedback, ultra high speed video recording and playback, or upgrading an available transmission channel from Full HD to Ultra HD video, can benefit from using the UHT JPEG encoder − decoder technology.
The UHT-JPEG-D IP core is based on a multiple internal processing engine − scalable parallel architecture. In a similar way to the UHT JPEG encoder, the input JPEG stream is split into chunks allocated to each of the decoding engines. This is done in a way which is totally transparent to the system utilizing the IP, abstracting all the parallelization complexity from the rest SoC components. The number of the available internal decoding engines is configurable, ergo the performance and the footprint of the design are scaled according to the application requirements. Rates up to 32 MSamples/MHz are possible by the UHT-JPEG-D architecture, enabling ultra high throughput even in low-cost FPGA devices.
The UHT JPEG decoder is strictly compliant to the ITU T.81 and ISO/IEC 10918-1 specifications. It supports 4:4:4, 4:2:2, 4:2:0 and 4:0:0 chroma sampling formats, in 8, 10 or 12 bits per component sample depth. The core uses a single compressed data input interface − accepting the standard compliant JPEG byte stream generated by the UHT-JPEG-E IP core − and produces decoded raw video data in interleaved raster scan format. Its operation is completely standalone, without needing any host processing power. The decoder can be implemented using only on-chip memory resources, while also using off-chip memory is natively supported.
Alma Technologies IPs are designed to ensure a fast and trouble-free integration in any FPGA or ASIC design. They are available either as standalone, high quality and implementation technology independent VHDL or Verilog RTL, or as optimized Netlists for Altera, Lattice, Microsemi and Xilinx FPGA and SoC devices.
About Alma Technologies
Alma Technologies is a semiconductor IP provider, developing high quality IP cores since 2001. Its products stand out for their engineering, being complete, easy-to-use and reliable IP solutions. Best-in-class technical support and a long track record of proven designs by more than 200 licensees provide Alma Technologies customers with the best service and value.
Learn more at: www.alma-technologies.com.