BANGALORE, India --, July 8, 2015 —Krivi Semiconductor has announced availability of its Alcor IO pad library platform for UMC’s 28nm technology. This IO platform supports a wide variety of interface standards such as DDR, LVDS, and Memory card super combo IO libraries. All these IO libraries are proven in test silicon for their compliance to respective electrical standards, ESD and latch-up performance. “Our specialty IO platform gives great flexibility to SoC and IP companies using UMC 28nm technologies to pick off-the-shelf IO pads that match or exceed best power, performance and area in industry”, said Sivaramakrishnan Subramanian, Co-founder and Senior Principal engineer at Krivi. He further added “We designed ESD protection network that achieved 2-8kV HBM and more than 10A CDM peak current performance in these libraries”.
Universal DDR IO pad library supports all popular DDR standards like DDR4, DDR3/3U/3L, LPDDR3, LPDDR2, HSTL class-I and RLDRAM-3 etc. This library works at a maximum speed of 2.667Gbps in HLP process technology and boasts of having industry's smallest foot-print. Additional area optimization cells in the library allow engineers to build PHY with smaller widths that can potentially save up to 25% area. Data retention feature enables deep low power operation, allowing the core and most of the IO supply to power down during DRAM self-refresh conditions. Power ramping sequence is made independent with the help of a voltage sensing cell in the library. This library is designed with an aggressive power target of receiving data at 1mW/Gbps. Small idle mode static power consumption is achieved by fast wake-up support of receiver.
LVDS and SubLVDS combo IO library have data input and output cells along with an in-built Bandgap voltage reference cell for biasing. This IO pad meets TIA/EIA-644-A and SMIA 1.0 Part 2: CCP2 Sub-LVDSstandards while working at top speed of 2Gbps and 1.6Gbps respectively.Differential input IO pad operates at rail to rail common mode voltage with a resolution of as low input differential voltage as 50mV. Differential output IO padallows higher speeds with better signal integrity due to an in-built near-end termination.
Memory card I/O pad supports interface signaling ranging from 1.2V to 3.3V while using 1.8V gate oxide IO devices. This bi-directional I/O pad supports eMMC and UHS-I SD card standards along with related similar standards. The library offers the end-user a choice of multiple drive strengths, slew rates and weak pull resistors.
SLVS, SubLVDS and SD UHS-II combo IO pad library is designed to meet JESD8-13, SMIA 1.0 Part 2: CCP2, and UHS-II SD card association standards witha top speed of 1.56Gbps.Silicon report for SLVS and UHS-II will be available in August 2015.
UMC 28HLP IO Alcor platform is ready to be licensed from Krivi. A fully characterized silicon report across all PVT conditions is provided along with the library.
"UMC has built a strong library, IP and design support environment for customers designing into our high volume production 28nm technology,” said Shih-Chin Lin, senior director of UMC’s IP & Design Support division at UMC. “With the addition of the IO Alcor platform from Krivi, our mutual customers now have access to a valuable resource that will allow them to seamlessly integrate a wide variety of high speed memory IO into their SoC design.”
Krivi Semiconductor is an upcoming IP company with deep expertise in DDR PHY, IO pad libraries and Analog clocking macros. Highly motivated engineering team at Krivi takes advantage of decades of successful mass volume IP creation experience to bring best-in-class AMS and wired interconnect PHY IP products. Our flexible business model combined with world class engineering team adds tremendous value to the customers in building their SoC within time and budget. For more information about Krivi visit www.krivisemi.com.