RISC-V shows advantages over x86 and ARM
EETimes (7/13/2015 07:00 AM EDT)
A recent Berkeley workshop highlighted advances with RISC-V, an open source core already showing architectural advantages over commercial x86 and ARM cores.
In late June, Berkeley held a workshop to get to know what research has been underway on RISC-V. RISC-V is an open instruction set architecture (ISA) originally developed at Berkeley and based on established reduced instruction set computing principles. It is a minimal, modular ISA ready for hardware implementation, freely available to both academia and industry.
The workshop was sold out with 120 attendees representing 30 companies and 20 universities. The Berkeley speakers were in the minority, with other speakers from Australia, England, India, Italy and Switzerland.
It appears RISC-V is experiencing a bandwagon effect. Conversations in the hallways suggested multiple commercial efforts may be underway. The speculation was primarily due to the very active participation from the commercial engineering community.
The workshop's program emphasized past work and achievements but put even more emphasis on future challenges and research directions to pursue. Motivating talks covering multiple areas are fundamental to any successful systems workshop and particularly one of this type.
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