MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive
Open Source Core Advances
RISC-V shows advantages over x86 and ARM
Saleh Elmohamed
EETimes (7/13/2015 07:00 AM EDT)
A recent Berkeley workshop highlighted advances with RISC-V, an open source core already showing architectural advantages over commercial x86 and ARM cores.
In late June, Berkeley held a workshop to get to know what research has been underway on RISC-V. RISC-V is an open instruction set architecture (ISA) originally developed at Berkeley and based on established reduced instruction set computing principles. It is a minimal, modular ISA ready for hardware implementation, freely available to both academia and industry.
The workshop was sold out with 120 attendees representing 30 companies and 20 universities. The Berkeley speakers were in the minority, with other speakers from Australia, England, India, Italy and Switzerland.
It appears RISC-V is experiencing a bandwagon effect. Conversations in the hallways suggested multiple commercial efforts may be underway. The speculation was primarily due to the very active participation from the commercial engineering community.
The workshop's program emphasized past work and achievements but put even more emphasis on future challenges and research directions to pursue. Motivating talks covering multiple areas are fundamental to any successful systems workshop and particularly one of this type.
E-mail This Article | Printer-Friendly Page |
Related News
- Yocto Project Welcomes New Members, Advances Open Source Embedded Systems Through Momentum
- LeWiz Open Source LVDS Transceiver Design
- New RISC-V processors address demand for open source and performance
- Milk-V Launches Milk-V Vega, the World's First RISC-V Open Source 10 Gigabit Ethernet Switch
- Industry Leaders Launch RISE to Accelerate the Development of Open Source Software for RISC-V
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024