0-In verification IP ensures that assertions written today will continue to work with evolving standards and third party tool support
SAN JOSE, Calif. - Aug 26, 2002 - Today 0-In Design Automation, the Assertion-Based Verification Company, announced the availability of a version of its CheckerWare® library and monitors that supports Sugar - the Accellera assertion language standard.
"0-In is committed to delivering assertion methods, tools, libraries, and monitors built on industry standards," said Emil Girczyc, 0-In president and CEO. "0-In's unique assertion library mapping technology ensures that CheckerWare products can rapidly adapt to changing standards. This technology enables all CheckerWare customers to deploy assertion-based verification today knowing that the assertions they write will continue to work with evolving standards and third party tool support."
0-In's CheckerWare library represents a family of complex assertion IP for on-chip interfaces and common register transfer language (RTL) structures such as arbiters, FSMs, and FIFOs. CheckerWare monitors capture and check the complete set of cycle-by-cycle protocol rules for complex industry standard buses, memory interfaces, and communication protocols including PCI-X, HyperTransport, PCI-Express, DDR SDRAM, POS-PHY, Utopia, and SPI-4.
CheckerWare with Sugar Support enables third party tools that support Verilog and Sugar, two industry language standards, to understand and operate with 0-In CheckerWare. For tools that do not support Sugar, an equivalent IEEE Verilog version of CheckerWare is available - enabling customers to seamlessly mix and match tools that do and do not support Sugar in their assertion-based verification (ABV) flow. CheckerWare with Sugar Support also enables designers to use 0-In's efficient pseudo-comment specification syntax to place these Sugar assertions inline within their Verilog code.
0-In Assertion-Based Verification Methodology
0-In delivers a comprehensive ABV solution that provides value throughout the design and verification cycle - from the block level to the chip and system level. Assertions placed within the internal RTL design structures and interfaces constantly monitor the RTL design for assertion violations and structural coverage feedback. 0-In's ABV methodology provides vendor-independent support for existing tools and standards in a customer's verification flow including testbenches, simulation, formal verification, hardware acceleration, and emulation platforms.
0-In CheckerWare library and monitors enable designers to rigorously validate that designs conform to standard industry protocols. 0-In's interoperable assertion infrastructure allows the 0-In assertion methodology to easily support future Accellera assertion standards.
0-In CheckerWare with Sugar Support is currently being used by pilot customers and is available immediately to 0-In Check-In partners. Customer shipment will commence with shipment of Sugar-enabled tools from 0-In partners.
0-In Design Automation, Inc. (pronounced "zero-in") develops and supports functional verification products that help verify multi-million gate application-specific integrated circuit (ASIC) and system-on-chip (SoC) designs. Twelve of the 15 largest electronics companies have adopted 0-In tools and methodologies in their integrated circuit (IC) design verification flows. 0-In was founded in 1996 and is based in San Jose, Calif. For more information, see http://www.0-in.com.
0-In® and CheckerWare® are registered trademarks of 0-In Design Automation, Inc.