English
Accellera Systems Initiative Announces SCE-MI 2.3
Updates give verification engineers more flexibility in their flows
Elk Grove, Calif., August 20, 2015 - Accellera Systems Initiative (Accellera), the electronics industry organization focused on electronic design automation (EDA) and intellectual property (IP) standards, announced today updates to the Standard Co-Emulation Modeling Interface (SCE-MI).
The newest version of the standard, SCE-MI 2.3, expands the set of SCE-MI compliant DPI function argument data types, giving users less restrictions and more opportunity for design portability; extends the debug interface to provide C-side access to HDL-side registers, making the design on the emulator more accessible and debug easier; and adds a new mechanism that enables a SystemVerilog HVL-side testbench to call DPI functions to HDL-side SystemVerilog and vice versa, removing limitations in emulation usage.
“The goal of the SCE-MI standard is to reduce the effort necessary to get a system into an emulation or prototyping environment for verification,” stated Brian Bailey, Interface Working Group chair. “With the new updates, we are removing restrictions, improving emulation debug capabilities and providing an enhancement to overcome unintended language limitations, giving users more flexibility in their verification flows.”
The Interfaces Working Group is seeking input on SCE-MI 2.3 from the community for consideration in the next revision of the standard. To provide feedback on SCE-MI 2.3, please send email to sce-mi-feedback@lists.accellera.org. To download SCE-MI 2.3 for free, visit the Accellera Downloads page.
About Accellera Systems Initiative
Accellera Systems Initiative is an independent, not-for profit organization dedicated to create, support, promote and advance system-level design, modeling and verification standards for use by the worldwide electronics industry. The organization accelerates standards development and, as part of its ongoing partnership with the IEEE, its standards are contributed to the IEEE Standards Association for formal standardization and ongoing change control. For more information, please visit www.accellera.org. Find out more about membership.
|
||||||
Related News
- Accellera Announces Standardization Initiative to Address Design Automation and Tool Interoperability for Functional Safety
- Accellera Systems Initiative advances the SystemC ecosystem with a new core language library
- Accellera Systems Initiative Delivers UVM 1.2 to IEEE for Standardization
- Accellera Systems Initiative UVM 1.2 Proceeds to IEEE Standardization
- Accellera Systems Initiative Forms Portable Stimulus Working Group
Breaking News
- UltraSoC and Canis Labs partner to secure the CAN bus
- Synopsys Announces Support of TensorFlow Lite for Microcontrollers on Energy-Efficient ARC EM and ARC HS Processor IP
- Domain Specific Accelerators Will Drive Vector Processing on RISC-V
- GOWIN Semiconductor Integrates their latest HDMI/DVI RX and TX IP into GOWIN EDA IP Generator
- Menta joins PROMISE Consortium under the Horizon 2020 Initiative of the European Commission
Most Popular
- TSMC Announces Intention to Build and Operate an Advanced Semiconductor Fab in the United States
- Synopsys Announces Support of TensorFlow Lite for Microcontrollers on Energy-Efficient ARC EM and ARC HS Processor IP
- GlobalFoundries Abandons Chengdu Wafer Fab
- The TSMC and Huawei Announcements Are Not as Linked as You May Think
- Synopsys Enables Tapeout Success for Early Adopters of Arm's Next Generation of Mobile IP
|
E-mail This Article | 
|
|
Printer-Friendly Page |