SiS Tapes Out Six-Million Gate, 533MHz Chip Using First Encounter
San Jose, Calif., August 27, 2002: Cadence Design Systems, Inc. (NYSE: CDN), the world's leading supplier of electronic design products and services, today announced that Silicon Integrated Systems (SiS) Corporation has standardized on Cadence® First Encounter®, a proven silicon virtual prototyping technology, for the design of complex graphics integrated circuits (ICs). First Encounter's successful management of timing-driven placement issues was critical to the fast tape-out of SiS' six million-gate, 3D graphics IC. This new, high-performance chip from SiS supports a 16-bit, bi-directional data bus at 533MHz operating frequency.
First Encounter was used to quickly create a silicon virtual prototype, a near tapeout-quality implementation of the chip which included detailed routes. The prototype gave the design team accurate visibility into the full chip's timing and routability at the very beginning of the physical design cycle. This in turn enabled predictable implementation of even a complex, high performance design. First Encounter has now been standardized in SiS' latest design flow.
"SiS has always worked aggressively to deliver high performance graphics chips to our customers," said Chris Lin, vice president of the Multimedia Products Division of SiS. "Cadence First Encounter's ability to create a timing- and routing-accurate prototype dramatically reduces the time it takes to complete our cutting-edge multimedia designs. With so much of modern IC physical characteristics now dependent on the interconnect, First Encounter's ability to leverage wire information within the prototype is a big advantage."
"Today's timing closure challenges can be met only if the designer has the knowledge of how the routing actually looks," said Eric Filseth, vice president of SP&R Marketing at Cadence. "We're extremely pleased that SiS, an industry leader, chose the First Encounter strategy for their silicon virtual prototyping requirements. We look forward to continuing to serve SiS' needs on large, high-performance SoC designs."
Silicon Integrated Systems Corp. (SiS), a leading core logic and graphics supplier, was founded in 1987 in the Hsin-chu Science-based Industrial Park in Taiwan. Combining a broad logic technology base (CPU, core logic, 3D graphics, connectivity) with advanced fab (0.18u/0.15u/0.13u), the company is well positioned to be a leader in system-on-a-chip (SoC). The company has been listed on the Taiwan Stock Exchange (TSE2363) since August, 1997. More information about SiS is available at www.sis.com .
Cadence is the world's largest supplier of electronic design technologies and services. Leading computer, networking, wireless, and consumer electronics companies use the company's solutions to design electronic systems and semiconductors down to nanometer scale. IEEE, the world's largest technical professional society, honored Cadence with its 2002 Corporate Innovation Recognition award. With approximately 5,500 employees and 2001 revenues of approximately $1.4 billion, Cadence has sales offices, design centers, and research facilities around the world. The company is headquartered in San Jose, Calif., and traded on the New York Stock Exchange under the symbol CDN. More information about the company, its products and services is available at www.cadence.com .
Cadence, the Cadence logo, and First Encounter are registered trademarks of Cadence Design Systems, Inc. All other trademarks are the property of their respective owners.