MILPITAS, CA, Sept. 29, 2015 –
Open-Silicon, a system optimized ASIC solution provider, announced today the industry's first High Bandwidth Memory (HBM) subsystem IP. The solution is available for 2.5D ASIC design, starts today and will also be made available as licensable Intellectual Property (IP). Building on 2.5D ASIC (SiP) design, packaging, and test methodologies already demonstrated in silicon as early as 2013, this development completes the critical components needed for the successful integration of HBM Gen2 memory into ASIC SiPs. The subsystem (comprising of the HBM Controller, PHY, and 2.5D interposer IO) addresses interoperability and 2.5D design, test, and SiP packaging challenges. The HBM IP is suitable for power and form-factor constrained systems in high-performance computing, networking, high-end consumer, and graphics applications.
"Our customers and prospects for HBM equipped ASICs are attracted to the completeness of the solution we offer as Open-Silicon. We are uniquely positioned to provide a fully optimized HBM ASIC platform solution by leveraging our experience with 2.5D ASIC design with our experience offering other high-bandwidth chip-to-chip and chip-to-memory interface IP like Interlaken and Hybrid Memory Cube (HMC)," said Hans Bouwmeester, Vice president of IP and Engineering Operations at Open-Silicon.
In compliance with the HBM-Gen2 JEDEC® standard, Open-Silicon's IP translates user requests into HBM command sequences (ACT, Pre-Charge) and handles memory refresh, bank/page management, and power management on the interface. Additionally, the IP includes the PHY and custom die-to-die IO needed to drive the interface between the logic-die and the memory die-stack on the 2.5D Interposer.
Breaking through the memory wall, Open-Silicon's HBM IP subsystem solution is designed to provide the highest performance and flexibility for integrating high-bandwidth memory directly into next-generation system-in-package (SiP) solutions. The company has a portfolio of IPs targeted for very high-bandwidth applications and is actively engaged with customers to integrate the new HBM subsystem IP into devices for applications targeting imaging and high-speed networking equipment.
"HBM will enable development of next generation of SoC and ASICs for density and bandwidth hungry systems," said Rich Wawrzyniak, Senior analyst for ASICs & SoC with Semico Research. "Comprehensive solutions like Open-Silicon's HBM Gen2 IP subsystem and 2.5D ASIC capability should drive down the cost of deployment and accelerate this transition."
For more information visit www.open-silicon.com/high-bandwidth-memory-ip or email us at IP@open-silicon.com.
About Open-Silicon
Open-Silicon transforms ideas into system-optimized ASIC solutions within the time-to-market parameters desired by customers. The company enhances the value of customers' products by innovating at every stage of design -- architecture, logic, physical, system, software and IP -- and then continues to partner to deliver fully tested silicon and platforms. Open-Silicon applies an open business model that enables the company to uniquely choose best-in-industry IP, design methodologies, tools, software, packaging, manufacturing, and test capabilities. The company has partnered with over 150 companies ranging from large semiconductor and systems manufacturers to high-profile start-ups, and has successfully completed 300 designs and shipped over one hundred million ASICs to date. Privately-held, Open-Silicon employs over 250 people in Silicon Valley and around the world. www.open-silicon.com