Digital Blocks I2C & SPI Controller IP Core Families Extend Lead in Sensor Interface to Host Processors with System-Level Features & Low Power
GLEN ROCK, New Jersey, Sept 30, 2015 – Digital Blocks, a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers with Embedded Processor & Peripherals requirements, extends its leadership in I2C and SPI Controller Verilog IP Cores targeting IC Sensor interfaces to Host Processors.
Digital Block separate I2C and SPI Controllers target both the Host Processor and the Sensor IC Interface to the I2C and SPI Buses. Digital Blocks Verification suite targets the following Sensor IC Applications:
- Accelerometers / Gyroscopes / Compass / Magnetometers
- Humidity, Gas/Chemical, Pressure, Temperature, UV Index, Ambient Light
- Capacitive Touch
- Proximity
- Digital Color
- Automotive, Medical, IoT, Wearables, SmartPhones
I2C and SPI Verilog IP Core Common Features are the following:
- Master/Slave, Master-only, & Slave-only I2C or SPI Controller Verilog IP
- Finite State Machine control unit to off-load the I2C or SPI transfer from the Processor
- TX, RX, TX/RX FIFO configuration options, dual clock design, parameterized depth
- CPU Interface via APB/AHB/AHB-lite/AXI4/AXI4-lite/AXI3/Avalon bus fabrics
- Similar Programming Architectures
- Low Power Design
Inter-Integrated Circuit (I2C) Controller Verilog IP Core Features are the following:
- Full range of I2C Bus Speeds: Standard mode (100 Kb/s), Fast mode (400 Kb/s), Fast mode plus (1 Mbit/s), Ultra-Fast-mode (5 Mbit/s) & Hs mode (3.4+ Mb/s)
- Multi-master, Arbitration, Clock Synchronization (Master Features)
- Enhanced SCL / SDA spike filtering capabilities
- SMBus Compatible (optional)
- HID over I2C (optional)
Serial Peripheral Interface (SPI) Controller Verilog IP Core Features are the following:
- SPI Bus Speeds programmable up to 150 Mbit/s
- Static SPI clock design for lowest power
- 4 and 3 wire SPI Interfaces
Price and Availability
The DB-I2C and DB-SPI IP Core Family are available immediately in synthesizable Verilog RTL, along with synthesis scripts, a simulation test bench with expected results, datasheet, and user manual. For further information, product evaluation, or pricing, please visit Digital Blocks at http://www.digitalblocks.com
About Digital Blocks
Digital Blocks is a leading developer of silicon-proven semiconductor Intellectually Property (IP) soft cores for system-on-chip (SoC) ASIC, ASSP, & FPGA developers with Embedded Processor & Peripherals, Display Controller, Display Link Layer, 2D Graphics, Image Compression, Audio / Video processing, and High-Speed Networking requirements.
Digital Blocks designs silicon-proven IP cores for technology systems companies, reducing customer’s development costs and significantly improving their time-to-volume goals. Digital Blocks is located at 587 Rock Rd, Glen Rock, NJ 07452 (USA). Phone: +1-201-251-1281; Fax: +1- 702-552-1905; Media Contact: info@digitalblocks.com; Sales Inquiries: info@digitalblock.com; On the Web at www.digitalblocks.com
|
Digital Blocks Hot IP
Related News
- Digital Blocks I2C & SPI Controller IP Core Families Extend Leadership in Sensor Interface to Host Processors with System-Level Features & Low Power
- Digital Blocks AMBA Peripherals I3C, I2C, eSPI, xSPI Controller IP Core Families Extend Leadership with enhancements containing feature-rich, system-level integration features.
- Digital Blocks Extends its I2C Controller IP Core Family with More Enhanced Capabilities & System-Level Features
- Digital Blocks Extends its I2C Controller IP Core Family with Enhanced Capabilities & System-Level Features
- Digital Blocks AMBA Multi-Channel DMA Controller IP Core Family Extends Leadership with releases for core DMA Engines in RISC-V® & ARM® Systems and Peripherals to Memory Applications
Breaking News
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
E-mail This Article | Printer-Friendly Page |