Synopsys Unveils New ATPG Technology Delivering 10X Faster Test Pattern Generation
Innovative, Efficient Engines Achieve Speed-Up While Reducing Pattern Count by 25 Percent
MOUNTAIN VIEW, Calif. -- Oct. 5, 2015 -- Synopsys, Inc. (Nasdaq: SNPS) today announced a new, breakthrough ATPG and diagnostics technology that delivers 10X faster run time and 25 percent fewer test patterns to shorten schedules, accelerate silicon debug and reduce test time and cost. Innovative, memory-efficient engines for test generation, fault simulation and diagnosis execute finely segmented threads on all available server cores, maximizing throughput while minimizing the number of patterns required to achieve targeted test coverage. Combined with Synopsys' DFTMAX™ compression, this new test technology will enable design teams to meet their test quality, time and cost goals with unprecedented speed.
"Increasingly complex SoC designs and shrinking schedules require fast turn-around for generating high-quality manufacturing test patterns," said Roberto Mattiuzzo, SoC integration and DFT methodologies manager in STMicroelectronics' Digital and Mixed Processes ASIC division. "Working with Synopsys on their new ATPG technology should produce faster ATPG run times and significantly fewer test patterns to help us test first-silicon samples sooner and minimize time on the tester. This technology will also help accelerate our ramp-up of dense and complex products in FD-SOI technology thanks to an even more efficient flow for our ASIC customers."
The new test generation, fault simulation and diagnosis engines are extremely fast, exceedingly memory efficient and highly optimized for generating patterns and executing fine-grained multithreading of the ATPG and diagnosis processes. These innovations lead to fewer test patterns and 10X faster runtime, enable utilization of all server cores regardless of design size and surpass previous technologies that are limited by high memory usage. Moreover, tight links with Synopsys' GalaxyTM Design Platform tools, such as Design Compiler® RTL Synthesis, PrimeTime® timing signoff and StarRCTM parasitic extraction, along with other Synopsys tools, including Yield Explorer® yield analysis and Verdi® automated debug system, deliver the highest quality test while minimizing turnaround time.
"Customers worldwide rely on Synopsys' synthesis-based test solution to achieve the highest test quality on their most challenging designs," said Antun Domic, executive vice president and general manager for Synopsys' Design Group. "This announcement demonstrates our commitment to continually deliver innovative and groundbreaking test technologies, and addresses our customers' need for faster ATPG and diagnostics as well as reduced silicon test time."
About the Synopsys Synthesis-Based Test Solution
The Synopsys synthesis-based test solution is comprised of SpyGlass® DFT ADV testability analysis, DFTMAX, DFTMAX Ultra and TetraMAX® power-aware logic test and silicon diagnostics offerings; the DesignWare® STAR Hierarchical System for hierarchical test of IP and cores on an SoC; the DesignWare STAR Memory System® solution for embedded test, repair and diagnostics; the Yield Explorer® tool for design-centric yield analysis; and the Camelot™ software system for CAD navigation. Synopsys' test solution combines Design Compiler RTL synthesis with embedded test technology to optimize timing, power, area and congestion for test as well as functional logic, leading to faster time-to-results. The Synopsys test solution delivers tight integration across the Synopsys Galaxy Design Platform, including Design Compiler, IC Compiler™ II place and route system, and PrimeTime, to enable faster turnaround time meeting both design and test goals, higher defect coverage and faster yield ramp.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 16th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP, and is also a leader in software quality and security testing with its Coverity® solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
|
Synopsys, Inc. Hot IP
Synopsys, Inc. Hot Verification IP
Related News
- DecaWave Deploys Synopsys TetraMAX II ATPG on Latest Automotive Design to Lower Test Time 50 Percent and Speed Runtime by 10x
- Synopsys Unveils New Synthesis-Based Test Technology Delivering Up to 3X Higher Compression
- Synopsys Unveils New IC Compiler Router Delivering 10X Speed-Up
- Cadence Introduces the Spectre X Simulator, a Massively Parallel Circuit Simulator Delivering Up to 10X Faster Simulation with the Same Golden Accuracy
- Synopsys Unveils TestMAX Family of Products to Address Critical and Evolving Test Challenges
Breaking News
- Silex Insight unleashes their new video codec (Colibri), that will shape the future of AV over IP distribution over 1GbE
- IAR Systems announces availability of RISC-V development tools with certification for IEC 61508 and ISO 26262
- proteanTecs Joins the TSMC IP Alliance Program
- BrainChip's Success in 2020 Advances Fields of On-Chip Learning and Ultra-Low Power Edge AI
- Revenue per Wafer Climbs As Demand Surges for 5nm/7nm IC Processes
Most Popular
- Verisilicon High-Performance and High-Quality AI Video Processor Powers Leading Datacenters
- AMD, TSMC & Imec Show Their Chiplet Playbooks at ISSCC
- Synopsys Delivers Breakthrough Performance with New ZeBu Empower Emulation System for Hardware-Software Power Verification
- Global Semiconductor Sales Increase 13.2% year-to-year in January
- Achronix and Mobiveil Announce Partnership to Deliver High-Speed Controller IP and FPGA Engineering Services
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |