Latest release enables rapid radio development and implementation on All Programmable FPGAs, SoCs & MPSoCs
SAN JOSE, Calif., Oct. 6, 2015 -- Xilinx, Inc. (NASDAQ: XLNX) today announced the 2015.3 release of System Generator for DSP, the industry's leading high-level tool for designing high performance DSP systems using Xilinx® All Programmable devices. With System Generator, algorithm developers can create production-quality DSP implementations within the familiar MATLAB® and Simulink® Model-Based Design environment in a fraction of the time compared to traditional RTL. The latest release delivers higher-level design abstractions and 7X greater design productivity for the development of wireless radio algorithms realized through a combination of a new blockset, faster simulation, and compilation run times.
Higher-Level Design Abstractions
With this new release, higher level design abstractions are enabled through HDL Coder interoperability with System Generator block hierarchies for use with Vivado® Design Suite. This allows a flexible mixture of high level and target optimized code to create the best implementation results. This new flow provides reusable data path implementations within System Generator that easily connects to system-on-chip (SoC) platforms containing JESD204 and CPRI interfaces and wireless radio IP like crest factor reduction.
"MathWorks continues to expand code generation, verification and platform support capabilities for targeting wireless radio algorithms to Xilinx FPGAs and All Programmable SoCs," said Jim Tung, Fellow at MathWorks. "The enhanced System Generator can be used with HDL Coder for rapid prototyping, creating production IP for use with Vivado IP Integrator, and simulating high-level behavioral algorithms and optimized IPs together in Simulink, significantly reducing time to market for our joint customers."
Enhanced Blockset Delivers 7X Faster Verification and Compilation
The usability of the System Generator blockset for digital up converters and digital down converters (DUC/DDC) has been greatly simplified for wireless algorithm development. Enhancements to improve verification and compile runtime have been added to the new blocks, all of which are configured with seven or fewer parameters. The digital FIR Filter block tightly integrates with the Filter Design and Analysis Tool from MathWorks to build area efficient filters, including fixed-fractional interpolation or decimation types. The Sine Wave and complex product blocks greatly simplify modulator design for frequency conversion at high sample rates. The requantize block enables quick manipulation of data types to maximize dynamic range at any point in the data path.
Faster Design Exploration and Iterative Design Closure
With the System Generator waveform viewer, developers can easily cross probe into the block across multiple clock domains. The new interactive cross probing accelerates design exploration and provides iterative design closure. With timing analysis cross probing, algorithm developers can quickly identify their critical paths and single out bottlenecks that may affect throughput and latency of their algorithms to make swift adjustments. Also new to this release are improvements to System Generator hardware-based co-simulation improving verification run time by 45X.
System Generator for DSP 2015.3 is available now with support for Xilinx® 7 series, UltraScale™ devices as well as early access support for UltraScale+™ FPGAs and MPSoCs. Download System Generator with the Vivado Design Suite 2015.3 at www.xilinx.com/download. Watch the Getting Started with System Generator QuickTake Video, sign up for training, and take advantage of the UltraFast Design Methodologies to jumpstart your productivity.
Xilinx is the leading provider of All Programmable FPGAs, SoCs, MPSoCs, and 3D ICs. Xilinx uniquely enables applications that are both software defined and hardware optimized – powering industry advancements in Cloud Computing, SDN/NFV, Video/Vision, Industrial IoT, and 5G Wireless. For more information, visit www.xilinx.com.