Locked in a race for a share of the communications components market, MoSys Inc. has developed a 36Mbit SRAM targeted at high-end data, telecommunications, and DSP applications.
The symmetric pipeline-burst SRAM operates at speeds of up to 200MHz, with a sub-3ns clock-to-data access time. Featuring a 1.8V memory core and either a 1.8 or 2.5V I/O, the MC8051M36 offers designers the best possible combination of system space and power, said Andre Hassan, vice president and general manager of memory products at MoSys, Sunnyvale, Calif.
"Unlike cache applications, where the read-and-write pipelines are optimized for the processor itself, communications applications prefer to be buffer-optimized," Hassan said. "The real unique thing about the symmetric pipeline is that read-and-write have the identical timing. This is a primary requirement in communications systems."
Communications applications tend to process bursts of information, "so a quick t urnaround becomes a lot more critical in a communications environment," said Bob Merritt, an analyst at Semico Research Corp. based in Redwood City, Calif.
SRAM makers for the past several years have been pursuing communications applications by developing high-speed parts capable of full bus utilization, Merritt said. Integrated Device Technology Inc., Santa Clara, Calif., for example, developed its Zero Bus Turnaround SRAM line, while San Jose-based Cypress Semiconductor Corp. has a version called No Bus Latency.
The competition to determine the next dominant SRAM is intensifying as worldwide SRAM shipments are expected to drop 25% this year, to $4.9 billion, vs. $6.5 billion in 2000, Merritt said. Revenue will continue to decline to $3.6 billion in 2005, according to Semico.
MoSys is sampling the MC8051M36 packaged in a standard 100-pin LQFP. Production quantities will be available in November. Pricing will vary depending on the device's speed. A 133MHz chip is $100.10 in 1,000-piece quantitie s.