GRENOBLE, France - September the 2nd, 2002 - In their lasting drive to support IC designers striving to meet the challenge of power-stingy Systems-on-chip (SoCs) with the highest design yield, Dolphin Integration, provider of state-of-the-art Silicon IP, is releasing a new design architecture for embedded RAM and ROM extending the frontiers of power optimization.
The new generation of design architectures for RAM (4G) and for ROM (5.5G) delivers the most competitive solutions for Fabless suppliers and Integrated Device Makers alike, relying on silicon-foundries or on proprietary fabrication lines, be they designing battery powered SoC or simply IC's so large that power dissipation becomes an issue.
The new generators for RAM - Flip-SpRAM-cLP-4G-XAM - and for metal programmable ROM - Flip-vROMet-cLP-5.5G - deliver instances up to 1 Megabit at 0.13 um of lithography. Under the worst case conditions for consumption (1.32 V, -40° C, Fast process), a Single-Port RAM instance of 256 kbits consumes only 40 uA/Mhz, while under the worst case conditions for speed (1.08 V, 125°C, Slow process) it runs faster than 200 MHz. Similarly, a single-layer programmable ROM (Via) of 1 Mbit consumes a mere 21 uA/Mhz, while running faster than 150 MHz. Furthermore, such RAM's and ROM's are functional down to 0.7 V with 100 % design yield.
Availability and Pricing
Generators for low-power RAM and ROM based on such advanced architectures are already available in 0.25 um, 0.18 um for most fabrication process variants. Generators for low-power RAM and ROM relying on the latest design architecture design will be available in the 4th quarter of 2002 for 0.13 um. Pricing of instances of Flip-SpRAM and Flip-vROMet starts as low as 15,000 Euro or US$ 15,000 (unique worldwide list price).
For further data, browse through: http://www.dolphin.fr/flip/ragtime/ragtime_flash.html