TEWKSBURY, Mass.-- November 10, 2015 --Northwest Logic Inc., a leader in high-performance digital IP Cores and Avery Design Systems, a leader in Verification IP (VIP) solutions, today announced that Northwest’s High Bandwidth Memory (HBM) Controller Core has been verified utilizing Avery’s HBM memory model. In addition, Northwest Logic is using Avery DIMM and component memory models as part of its DDR4 Controller Core verification.
Northwest Logic offers high-performance, full-featured, easy-to-use HBM, DDR4/3/2/1 and LPDDR4/3/2/1 Memory Controller Cores. These cores are highly configurable to enable customers get a Memory Controller solution which meets their specific needs with a minimal amount of size, latency and cost. These cores have been widely used in a variety of application including Storage, Networking and High-Performance Computing.
"We use the memory models included in the Avery's HBM-Xactor and DDR-Xactor VIP as a key part of our Memory Controller verification," said Brian Daellenbach, president of Northwest Logic. These models enable us to comprehensively verify our Memory Controller Cores. We have found the memory models and associated support to be very high quality. We recommend Avery’s VIP to all our customers for robust SoC verification."
The VIP includes a wide range of models including HBM and RDIMM/LDRDIMM memory modules models including fully functional RCD2 and DB2, DDR/LPDDR memory chip models, DFI-based PHY model and HBM and DDR/LPDDR host memory controller models. These models are useful in a broad range of SoC, PHY and DIMM developments.
Memory models for HBM, DDRx, LPDDRx, and LRDIMM support comprehensive protocol and timing checks, advanced timing features, protocol analyzer trace reports, and performance interposer functions which indicate min/max, median, and mean latencies including bank group analysis and DQ utilization and bandwidth.
The HBM and DDR/LPDDR host memory controller VIP models support PHY and DIMM development including features to randomly configure DDR and LRDIMM for comprehensive operational coverage, performs complete DDR, RCD and DB initialization and training mode sequences based on JEDEC raw card trace length delays including random skew and tolerance. Users develop high-level read/write sequences for the memory controller VIP which then automatically sequences commands including auto activation, precharge, and refresh and spaces commands according to operational timing parameters. Avery also supports compliance testsuites for PHY and LRDIMM verification.
The VIP is 100% vative SystemVerilog UVM and portfolio licensing options provide the cost efficient and flexible usage models.
Visit us at the DVCon Europe, November 11-13, in booth #E2 to learn more about Avery VIP solutions.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, USB, AMBA, UFS, MIPI, DDR/LPDDR, HBM, HMC, ONFI/Toggle, NVM Express, SCSI Express, SATA Express, eMMC, SD/SDIO, and CAN FD standards. The company is a member of the Mentor Graphics Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
About Northwest Logic
Northwest Logic, founded in 1995 and located in Beaverton, Oregon, provides high-performance, silicon-proven, easy-to-use IP cores including high-performance PCI Express solution (PCI Express 3.0, 2.1 and 1.1 cores and drivers), Memory Interface Solution (DDR4/3/2, LPDDR4/3/2 SDRAM; HBM, MRAM, RLDRAM 3/II), and MIPI Solution (CSI-2, DSI). These solutions support a full range of platforms including ASICs, Structured ASICs and FPGAs. For additional information, visit www.nwlogic.com .