Achieves 5 Percent Smaller Area with Accelerated Design Closure
MOUNTAIN VIEW, Calif., Dec. 14, 2015 -- Synopsys, Inc. (Nasdaq: SNPS) today announced that Axell, a leading fabless design company of graphics chips for interactive entertainment and industrial embedded systems, has switched to Synopsys' Design Compiler® RTL synthesis solution for their IC designs. Achieving smaller die area with high engineering productivity are critical goals for Axell to deliver competitive products to their target markets. To achieve these goals, Axell evaluated available RTL synthesis solutions and selected the Design Compiler solution, including DC Explorer, based on results delivering 5 percent area reduction coupled with high design performance and fast runtime.
"With their next-generation interactive entertainment products requiring higher resolution graphics capabilities, our customers are looking to Axell to deliver increasing design performance with improved cost effectiveness," said Atsushi Kikuchi, senior manager at Axell Corporation. "Following an evaluation of available RTL synthesis solutions, we selected Synopsys' Design Compiler as a result of its ability to shrink our design size by 5 percent while achieving fast design closure. We are also adopting DC Explorer to give us additional capabilities for fast, early RTL exploration to quickly and efficiently perform what/if analyses of various design configurations before committing to our final design. We are deploying these tools for our next-generation chips targeting an advanced manufacturing process."
Synopsys' Design Compiler family of products maximizes design productivity with its complete solution for RTL synthesis and test. Underpinning the Design Compiler family, the DC Ultra™ synthesis solution concurrently optimizes for timing, area, power and test and includes topographical technology to reduce costly design iterations. DC Explorer enables early RTL and floorplan exploration to accelerate development of high-quality RTL and constraints, leading to faster synthesis and place and route. Design Compiler Graphical uses advanced optimizations and shared technology with the IC Compiler™ and IC Compiler II place and route solutions to deliver best-in-class quality of results for the most challenging designs at all process nodes. In addition, Design Compiler Graphical enables RTL designers to predict, visualize and alleviate routing congestion and to perform floorplan exploration prior to physical implementation. Design Compiler Graphical also produces physical guidance to IC Compiler and IC Compiler II that tightens timing and area correlation and speeds-up placement runtimes. For further information visit: http://www.synopsys.com/tools/implementation/rtlsynthesis/Pages
"In the interactive entertainment and industrial embedded systems markets that Axell serves, high performance and cost effectiveness are key ingredients for their product success," said Bijan Kiani, vice president of marketing for Synopsys' Design Group. "Design Compiler's advanced optimization technologies coupled with DC Explorer's early RTL analysis capabilities enable Axell to achieve design size reduction while meeting the high performance required for their customers' next-generation products."
Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 16th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software quality and security solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.