Area-optimized design shows 38% shrink
Rick Merritt, EETimes
2/4/2016 08:00 AM EST
SAN FRANCISCO – Samsung gave a peek at its 10nm finFET technology and an advanced 128 Mbit SRAM made in the process in a paper at the International Solid-State Circuits Conference (ISSCC) here.
A version of the new 6T SRAM bitcell optimized for size is 38% smaller than a similar part in Samsung’s 14nm process. It measures 0.040mm2 compared to 0.049mm2 for a version optimized for high current.
SRAMs take up as much as 30% of mobile applications processors and smaller size is generally a welcome indication of lower cost per transistor, Samsung noted. However in the case of the 10nm SRAM, small size created a problem.
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