Availability of 14-nm Runsets Provides Benefits of In-Design Productivity and Faster Physical Verification
MOUNTAIN VIEW, Calif. -- Feb. 11, 2016 -- Synopsys, Inc. (Nasdaq:SNPS) today announced that Synopsys' IC Validator physical verification product has been certified by Samsung Foundry for all designs using its 14-nanometer (nm) manufacturing processes, Samsung Foundry's most advanced technology currently in production. With this certification, Samsung Foundry customers are enabled with the efficiency advantages of IC Validator and can now verify their designs with full confidence that the tool and the runsets have been certified by Samsung Foundry for the highest level of accuracy. The certified runsets, including design rule checking (DRC), layout-versus-schematic (LVS) and metal fill technology files, are immediately available from Samsung Foundry, ensuring a high level of manufacturability compliance and enabling design for maximum yield.
IC Validator, part of the Synopsys Galaxy™ Design Platform, is a comprehensive and highly scalable physical verification tool suite including DRC, LVS, extended electrical rule check (ERC), metal fill and DFM enhancement. IC Validator uses its scalable hybrid data and command-processing engine as a powerful platform for coding and validating the complex polygon and edge-based rules required for emerging process nodes. IC Validator enables coding at higher levels of abstraction and is architected for near-linear scalability that maximizes utilization of mainstream hardware, using smart memory-aware load scheduling and balancing technologies. These capabilities enable Samsung Foundry to streamline design rule development and deployment as well as provide mutual customers with the high accuracy and excellent scalability needed for leading-edge process nodes.
IC Validator is also an ideal add-on to the IC Compiler™ II system for In-Design physical verification. In-Design is enabled by the intelligent integration of IC Validator and IC Compiler II, making it possible for place-and-route engineers to perform independent signoff-quality analysis earlier, before the design is finalized and while correction can be automated. In-Design technology enables new high-productivity functionality, such as automatic DRC repair, timing-aware metal fill and rapid ECO validation, all within the place-and-route environment. In-Design physical verification eliminates expensive iterations with downstream analysis tools and maintains a convergent design flow to physical signoff.
"As manufacturing complexity is placing increased challenges on designers to deliver within schedule, it is extremely important that we continue to collaborate closely with leading foundries like Samsung," said Bijan Kiani vice president, product marketing, Design Group at Synopsys. "This certification demonstrates how designers with the most demanding designs are driving the market towards better signoff verification solutions that are also closely integrated into their design flows."
Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 16th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software quality and security solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.