By Peter Clarke, EETimes Europe
February 25, 2016
French researchers have developed a IP for deep neural networks that is available for licensing to run in software, for implementation in FPGA fabric, for synthesis within an SoC.
The Pneuro Engine is a multipurpose energy-optimized accelerator designed for neural networks and image processing chains. It utilizes a clustered SIMD architecture optimized for MAC operations (as found in SIMD extensions of popular processor architectures) but with a distributed memory optimized for near neighbourhood accesses and design reuse management.
The research team is from CEA List based at Saclay-Paris and at Embedded World demonstrated the use of an FPGA-based Pneuro on a GlobalSensing Technologies board to perform face recognition. The same technology has also been ported to a Raspberry Pi 2B containing a quad-core Cortex-A7, and to an Odroid XU3 board based on a quad Cortex-A15 processor.