Arasan Announces USB 2.0 PHY in Ultra Low Power TSMC 40LP
March 7, 2016, San Jose, CA -- Arasan’s USB 2.0 PHY has been designed to target mobile devices and the automotive market. This IP expands Arasan’s library of nodes, now available from 180nm to 28nm from major foundries including automotive grade qualifications. Ubiquitous in PCs, USB 2.0 is now the charging and media transport interface for billions of mobile products from Smartphones to headphones. USB is pervasive in all electronic segments including automotive, enterprise, medical and industrial applications.
Arasan entered the USB 2.0 PHY IP market with the acquisition of the silicon-proven Mentor technology. Arasan engineering successfully integrated the technology into Arasan’s design flow to ensure interoperability with its controllers. Arasan is the only company to offer the complete suite of USB 2.0 IP products including the USB 2.0 Host, Hub, Device, OTG, and PHY. Arasan also offers the HSIC option for chip to chip connections over USB.
“With 20 years of USB experience and over 100 USB Semiconductor Licensees, Arasan is the Total USB IP Solution provider”, Chari Santhanam, Arasan VP. of Engineering and a recognized expert on USB IP.
Availability
Arasan’s USB 2.0 IP PHY and USB 2.0 controller IP are available for immediate delivery. Contact Arasan for more information.
About Arasan
Arasan Chip Systems is a leading provider of Total IP Solutions for mobile and the next generation of Smart applications from home to automobile. Arasan’s high-quality, silicon-proven, Total IP Solutions include digital IP cores, analog PHY interfaces, verification IP, hardware verification kits, protocol analyzers, software stacks and drivers, and optional customization services for Ethernet, MIPI, PCIe, USB, UFS, SD, SDIO, eMMC, and UFS. Arasan’s Total IP products serve system architects and chip design teams in applications that require silicon-proven, validated IP, delivered with the ability to integrate and verify both digital, analog and software components in the shortest possible time with the lowest risk.
|
Arasan Chip Systems Hot IP
Related News
- Synopsys Unveils 30 Percent Smaller Area, Low Power USB 2.0 PHY IP for 28-nm Processes
- USB 4.0, USB 3.2, USB 3.0, USB 2.0 Silicon Proven PHYs in TSMC, UMC & SMIC Foundries available from T2MIP
- Arasan announces the immediate availability of its Ultra Low Power MIPI D-PHY IP Compliant to D-PHY Specification v1.20 for TSMC 22nm SoC Designs
- SMSC Launches Industry's First, Hi-Speed Inter-Chip USB 2.0 to 10/100 Ethernet Controller for Low Power Applications
- Arasan Chip Systems Announces Mixed Signal USB 2.0 PHY IP
Breaking News
- Thalia's AMALIA 24.2 introduces pioneering estimated parasitics feature to reduce PEX iterations by at least 30%
- TSMC plans 1.6nm process for 2026
- Qualitas Semiconductor Partners with TUV Rheinland Korea to Enhance ISO 26262 Functional Safety Management System
- M31 has successfully launched MIPI C/D PHY Combo IP on the advanced TSMC 5nm process
- Ceva multi-protocol wireless IP could simplify IoT MCU and SoC development
Most Popular
- Controversial former Arm China CEO founds RISC-V chip startup
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Credo at TSMC 2024 North America Technology Symposium
- Synopsys Accelerates Next-Level Chip Innovation on TSMC Advanced Processes
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
E-mail This Article | Printer-Friendly Page |