SAN JOSE, Calif., 14 Mar 2016 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that it has collaborated with Mellanox Technologies (NASDAQ: MLNX) to demonstrate multi-lane interoperability between Mellanox’s physical interface (PHY) IP for PCIe 4.0 technology and Cadence’s 16Gbps multi-link and multi-protocol PHY IP implemented in TSMC’s 16nm FinFET Plus (16FF+) process. Customers seeking to develop and deploy next-generation green data centers can now use a silicon-proven IP solution from Cadence for immediate integration and fastest market deployment. Cadence and Mellanox are scheduled to demonstrate electrical interoperability for PCIe 4.0 architecture between their respective PHY solutions at the 2016 TSMC Symposium on March 15, 2016 in Santa Clara, California.
Cadence and Mellanox obtained the 16Gbps results with four lanes running traffic concurrently, a typical configuration for next-generation servers, storage and networking equipment. Mellanox and Cadence designed a PHY that exceeds PCIe 4.0 architecture requirements in terms of insertion loss, while demonstrating a bit-error rate (BER) below 10-15. Cadence also offers silicon-proven Algorithmic Modeling Interface (AMI) models for use with the company’s Sigrity™ technologies to create chip, package and board designs that deliver robust signal integrity to handle impairments such as crosstalk and insertion loss deviation. For more information on Cadence’s IP offering for PCIe 4.0 technology, visit www.cadence.com/news/pcie4.
“PCIe 4.0 technology throughput will enable data center applications to analyze more data and to find insights in real time,” said Gilad Shainer, vice president of marketing at Mellanox Technologies. "The successful interoperability with Cadence shows the increase in the PCIe 4.0 ecosystem of hardware solutions, and marks an important milestone toward building InfiniBand or Ethernet connected data centers based on the PCIe 4.0 specification.”
“As an active PCI-SIG member, Cadence continues to innovate and develop IP that supports the latest PCIe specifications,” said Hugh Durdan, vice president of marketing for Design IP at Cadence. “Our collaboration and successful interoperability demonstration with Mellanox gives our customers peace of mind in knowing that they can incorporate Cadence IP for PCIe 4.0 technology into their designs successfully and with less risk.”
Mellanox Technologies is a leading supplier of end-to-end InfiniBand and Ethernet interconnect solutions and services for servers and storage. Mellanox interconnect solutions increase data center efficiency by providing the highest throughput and lowest latency, delivering data faster to applications and unlocking system performance capability. Mellanox offers a choice of fast interconnect products: adapters, switches, software, cables and silicon that accelerate application runtime and maximize business results for a wide range of markets including high-performance computing, enterprise data centers, Web 2.0, cloud, storage, telecom and financial services. More information is available at www.mellanox.com.
Cadence enables global electronic design innovation and plays an essential role in the creation of today’s integrated circuits and electronics. Customers use Cadence® software, hardware, IP and services to design and verify advanced semiconductors, consumer electronics, networking and telecommunications equipment, and computer systems. The company is headquartered in San Jose, Calif., with sales offices, design centers and research facilities around the world to serve the global electronics industry. More information about the company, its products and its services is available at www.cadence.com.
PCI-SIG is the consortium that owns and manages PCI specifications as open industry standards. The organization defines industry standard I/O (input/output) specifications consistent with the needs of its members. Currently, PCI-SIG is comprised of nearly 800 industry-leading member companies. To join PCI-SIG, and for a list of the Board of Directors, visit www.pcisig.com.