Mar 28, 2016 -- INNOSILICON, a word class, fabless design company focusing on high-speed PHY and mixed-signal IP, proudly announces the world’s first DDR4/LPDDR4 PHY & Controller IP combination that has been successfully proven in GLOBALFOUNDRIES 14nm LPP process. This DDR interface solution, which is backwards compatible to DDR3/LPDDR3, maintains low power, high performance and a small form factor. What’s more, our IP combination is optimized for the RAM market, satisfying the demanding data bandwidth requirements of various applications including mobile, cloud computing and networking.
Performance of this IP combination in wirebond configuration can reach speeds up to 2667 Mbps, and flipchip implementations will be even faster. Leveraging a choice of DFI V2.0/V2.1/V3.0/V3.1 standards, the PHY can be integrated either with our companion memory controller or any major 3rd party controller offering. In addition, customization and integration service are always available.