September 24, 2002, Communications Design Conference, San Jose, Calif., -- Leopard Logic, Inc. today launched the latest release of its ToolBlox suite of development tools and design kits for its HyperBlox FP embedded FPGA cores.
ToolBlox 2.3 introduces a design kit for the Synopsys® Design Compiler™ synthesis tool, supported by HyperBlox FP specific libraries. Sample synthesis scripts are provided as templates that have been tuned to maximize the performance of the design after layout with ToolBlox. An engineer experienced with the synthesis tools can be productive in less than a day. ToolBlox 2.3 is supported on Solaris and Windows platforms.
This new release makes it easy for Synopsys users to integrate an embedded FPGA core into their existing SoC (System-on-Chip) design flow. Designs are partitioned at the RTL level into modules that will be implemented in standard cells, and modules that are implemented in the HyperBlox FP cores. During synthesis, Design Compiler loads the appropriate cell library and optimizes the design for the respective target technology.
Once synthesis is complete, a gate level netlist is written in Verilog format and passed on to ToolBlox, which smoothly packs, places, and routes the synthesized gates into Leopard Logic's HyperBlox FP cores. The user simply defines the location of the output files and runs the tools. Users can choose between an easy-to-use GUI flow that walks the user through the entire process, or a command line interface that can be utilized in a script-driven design flow.
The ToolBlox design flow enables designers to quickly and easily synthesize and lay out an RTL design for placement in Leopard Logic's configurable logic cores. The flow supports all of Leopard Logic's HyperBlox device families of embedded FPGA cores and seamlessly interfaces with leading third party design tools via industry-standard data exchange formats such as Verilog, EDIF and SDF. This interoperability minimizes the learning curve and costs for customers adopting ToolBlox and HyperBlox.
The ToolBlox design flow encompasses the following key steps:
1. Synthesis & Simulation
HyperBlox users can use their design tools of choice by using the appropriate design kit. Design kits are available for leading ASIC synthesis and simulation tools.
2. ToolBlox Packer
The ToolBlox Packer uses advanced timing-driven optimization algorithms to optimize the packing of the synthesized ASIC gates into the HyperBlox core cells. User's can control the results of the packing process through numerous settings to either minimize the area or maximize the performance of the design.
3. ToolBlox Place & Route
The ToolBlox Place & Route tools facilitate quick assembly of the cells into the core, optimizing device performance while monitoring, and limiting routing congestion. Using Leopard Logic's proprietary "Reverse Routing" technology, the router quickly completes routing even of the most complex designs. The number of routing resources utilized are reduced to a minimum, ensuring the highest level of routing completions at high device utilization, regularly in excess of 90%. Once a design is fully placed & routed, the tools create a bitstream for download into the device. At the same time, an SDF file is produced to support static timing analysis and timing simulation to validate the performance and functionality of the design under worst–case timing conditions.
About Leopard Logic, Inc.
Leopard Logic™ provides embedded programmable logic solutions that increase performance and flexibility while reducing risk and system costs for System-on-Chip devices. Used to create next generation programmable device platforms, Leopard Logic's HyperBlox™ configurable logic cores are ideally suited for DSP or packet processing intensive applications, targeting markets like communications and digital consumer. The cores are silicon proven in leading manufacturing processes from TSMC and are delivered with a comprehensive integration package, including a suite of optimized software tools, enabling rapid integration with industry standard design flows and third party EDA tools. For more information visit www.leopardlogic.com.