ARM should unveil a new version of its Amba on-chip bus architecture in October. The bus has become a widely accepted interconnect standard for system-on-chip (SoC) design.
Amba 2.0 was released in May 1999 and is so widely used that even competitors such as MIPS Technologies have taken it up. ARM is now working with partners to develop Amba 3.0.
Simon Segars, executive vice- president of engineering at ARM, said: "We're looking at the bus requirements for large SoCs in future; what it takes to build a higher performance interconnect fabric."
He says that as SoCs start using multiple processors on-chip, the interconnect may need to provide the sideband signals necessary for keeping maintaining system coherency.
Segars says the Amba 3.0 architecture is also likely to include a lot of hierarchy and a partitioned bus structure to avoid wasting bandwidth by broadcasting all messages across the entire bus.
Jonathan Morris, plat forms program manager at ARM, said: "It's fair to say a lot of activity has been going on working towards another turn of the spec."
He says the new specification will continue the progress of ARM's on-chip bus, which has developed from the ARM System Bus (ASB) to Amba 2.0 in 1999, which introduced the ARM Hardware Bus (AHB).
This was followed in 2001 by variants which included multi-layer AHB and AHB Lite.
"AHB has done really well and established itself as a de facto standard," said Morris.
He stresses that ARM is not abandoning AHB with the new Amba: "There will be a compatibility story with AHB. The new standard will move forward a long way, but we will provide the support and infrastructure so AHB and the new standard can co-exist."
ARM is thinking about using Amba 3.0 to match the requirements of high-performance co-processors such as its MBX embedded 3D graphics cores. The company's roadmap for MBX implementations shows variants of the MBX core coupl ed with 64bit versions of Amba 3.0 as concepts for the first half of next year.