GRENOBLE, France - September the 24th, 2002 - Thanks to its competencies both as a Virtual Component provider and as an EDA provider, Dolphin Integration provides its customers with innovative solutions to facilitate the integration and verification of Virtual Components within a System-on-Chip.
IBM's FoCs which is a converter from the Sugar assertion language to the Verilog and Vhdl design languages, combined with Dolphin's SMASH, a single engine mixed signal multi level simulator, enables designers to develop checkers in SUGAR and integrate them both in Verilog and VHDL simulations.
It thereby provides assertion checks beyond the mere testbench and enabling verification throughout SoC integration. Furthermore, the non exhaustiveness of behavioral models is no longer a problem as rules which are too difficult to verify in the models can now be provided as add-on checkers, for instance to verify that synchronisation signals meet the specifications.
Thus, SUGAR checkers extend the SMASH Platinum simulator dynamic Electrical Rules Checking to dynamic Specification Rule Checking (dSRC(TM)), paving the way for future extensions to analog & mixed signal verification.
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