MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive
Do not miss the Green Thursday offering for ultra Low-Power SoCs at 55 nm
Grenoble, France - June 23, 2016 -- Leading-edge More-Than-Moore process variants at 55 nm for the challenges of IoT and wearable devices deserve equally state-of-the-art low power design methodologies: it involves Silicon IPs for embedding the Power Regulation Network and for the SoC Mode Control Network, together with the transfer of know-how to ensure a safe and smooth design-in.
Designers of low-power SoCs targeting 55 nm are proposed two self-contained kits, of Silicon IPs, with design methodologies, at a very attractive price up until the Green Thursday, June 30. Each kit is tailored to a major SoC challenge:
- For SoCs mostly in sleep mode: Power Regulation & Control Network kit
- For high duty-cycle SoCs: Voltage Regulation Network kit
REQUEST A “GREEN THURSDAY” QUOTE VALID UNTIL JUNE 30,2016
Such kits may be complemented with Foundation, Fabric and Feature IPs – such as standard cell libraries, memory generators, WhisperTrigger voice activity detector, uLP oscillators… – to combine the best power consumption, whatever the mode of activity of the SoC, with the smallest silicon area.
A catalog providing an overview of this consistent offering of Silicon IPs in 55 nm is immediately available on request.
About Dolphin Integration
DOLPHIN Integration contributes to "enabling low-power Systems-on-Chip" for worldwide customers - up to the major actors of the semiconductor industry - with high-density Silicon IP components best at low-power consumption.
"Foundation IPs" includes innovative libraries of standard cells, register files and memory generators as well as an ultra-low power cache controller. "Fabric IPs" of voltage regulators, Power Island Construction Kit and their control network MAESTRO enable to safely implement low-power SoCs with the smallest silicon area. They also star the "Feature IP": from ultra-low power Voice Activity Detector with high-resolution converters for audio and measurement applications to power-optimized 8 or 16 and 32 bit micro-controllers.
Over 30 years of experience in the integration of silicon IP components, providing services for ASIC/SoC design and fabrication with its own EDA solutions, make DOLPHIN Integration a genuine one-stop shop addressing all customers' needs for specific requests.
It is not just one more supplier of Technology, but the provider of the DOLPHIN Integration know-how!
|
Dolphin Design Hot IP
Related News
- LeapMind's Ultra Low-Power AI accelerator IP "Efficiera" Achieved industry-leading power efficiency of 107.8 TOPS/W
- Microchip Adds Second Development Tool Offering for Designers Using Its Low-Power PolarFire RISC-V SoC FPGA for Embedded Vision Applications at the Edge
- T2M announces Industry's first Ultra Low-Power Bluetooth Dual Mode RF IP on TSMC 22nm.
- Imec combines advanced machine learning algorithms and innovations in chip design to achieve cm accuracy and low-power ultra wideband localization
- Vidatronic Announces ACCUREF Series of Ultra-Precise, Extremely Low-Power Voltage and Current Reference IP Cores
Breaking News
- PUFsecurity Unveils Next-Gen Crypto Coprocessor PUFcc7 Featuring High-speed Performance and TLS 1.3 Support
- SEMIFIVE Starts Mass Production of its 14nm AI Inference SoC Platform based Product
- VeriSilicon's complete Bluetooth Low Energy IP solution is fully compliant with LE Audio specification
- TASKING and Andes Announce FuSa Compliant Compiler Support for Andes RISC-V ASIL Compliant Automotive IP
- Efabless Launches an "AI Wake Up Call" Open-Source Silicon Design Challenge
Most Popular
- Qualitas Semiconductor and Ambarella Sign Licensing Agreement
- ZeroPoint Technologies Signs Global Customer to Bring Hardware-Accelerated Compression to Hyperscale Data Centers
- Chiplet Interconnect Pioneer Eliyan Closes $60 Million Series B Funding Round, Co-led by Samsung Catalyst Fund and Tiger Global Management to Address Most Pressing Challenge in Development of Generative AI Chips
- Intel and Arm Team Up to Power Startups
- Alphawave Semi and InnoLight Collaborate to Demonstrate Low Latency Linear Pluggable Optics with PCIe 6.0® Subsystem Solution for High-Performance AI Infrastructure at OFC 2024
E-mail This Article | Printer-Friendly Page |