Samsung and Synopsys Collaborate to Reduce FinFET Layout Time
MOUNTAIN VIEW, Calif. -- Oct. 24, 2016 -- Synopsys, Inc. (Nasdaq: SNPS) today announced that its Custom Compiler™ tool has been certified by Samsung Electronics Co., Ltd. to support their 10-nanometer (nm) LPP (Low Power Plus) process. This included providing and validating a Custom Compiler process design kit (PDK) in the industry-standard iPDK format. The kit is available on request from Samsung.
The newly developed Samsung 10LPP iPDK includes all technology information needed to create schematics and layout for customer designs using the Custom Compiler tool with Samsung's 10LPP process. This comprehensive kit includes support for the groundbreaking Custom Compiler visually-assisted automation flow. Custom Compiler features enabled by the kit include full coloring for triple-patterning, fast placement of FinFET device arrays with the Symbolic Editor, in-design resistance and capacitance reporting during layout, and high-performance in-design design rule checking (DRC).
"We worked with Synopsys to include Custom Compiler support for Samsung's foundry process offerings," said Jaehong Park, senior vice president of the Design Service Team at Samsung Electronics. "This new 10LPP iPDK adds to our existing portfolio of iPDKs that are available for Synopsys Custom Compiler users."
Unified with Synopsys circuit simulation, physical verification and digital implementation tools, Custom Compiler technology provides Samsung 10LPP process users with a comprehensive custom design solution that reduces FinFET layout time.
"Custom Compiler users include leading-edge customers that demand support for the latest process technologies," said Bijan Kiani, vice president of product marketing at Synopsys. "Samsung and Synopsys worked together to enable Custom Compiler for Samsung's 10LPP process, which can shorten layout time from days to hours."
About Custom Compiler
Custom Compiler provides an open environment spanning schematics, simulation analysis and layout. Unified with Synopsys' circuit simulation, physical verification and digital implementation tools, Custom Compiler provides a comprehensive custom design solution. Custom Compiler shortens the time it takes to complete FinFET design tasks from days to hours. Its visually-assisted automation leverages the graphical use model familiar to layout designers while eliminating the need to write complicated code and constraints. With Custom Compiler, routine and repetitive tasks are dealt with automatically without extra setup. Custom Compiler's visually-assisted automation provides four types of assistants: Layout, In-Design, Template and Co-Design. Layout Assistants speed layout with user-guided automation of placement and routing. In-Design Assistants reduce design iterations by catching physical and electrical errors before signoff verification. Template Assistants help designers reuse existing know-how by making it easy to apply previous layout decisions to new designs. Co-Design Assistants combine the IC Compiler™ place-and-route solution and Custom Compiler into a unified solution for custom and digital implementation. Custom Compiler is based on the industry standard Open Access database. For more information about Custom Compiler, visit www.customcompiler.info.
Synopsys, Inc. (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world's 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP and is also growing its leadership in software quality and security solutions. Whether you're a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.