Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's highest performance Verilog simulator. The new release contains built-in comprehensive coverage analysis, enabling design teams using VCS to determine their verification quality before tapeout. In addition, Synopsys has added VCS DirectC, a new interface to accommodate the use of C/C++ models within a Verilog verification environment.
``Synopsys has integrated coverage analysis and the DirectC interface into the VCS engine to boost overall verification productivity of our customers,'' said Manoj Gandhi, senior vice president and general manager of the Verification Technology Group at Synopsys. ``We continue to innovate to provide the fastest Verilog simulator and the smartest and most productive verification environment.''
Coverage metrics are an industry-accepted measure of simulation effectiveness. As a standard part of VCS, designers will now have access to comprehensive built-in coverage analysis, including condition, toggle, line and finite-state-machine coverage. Using these capabilities built into the VCS engine, design teams can easily determine the quality or ``coverage'' of their verification tests. With the latest VCS release, designers only need to compile once to run both simulation and coverage analysis. As a result of this single compilation, users will see substantially better compile and run-time performance than with previous point tool solutions that use the Verilog Programming Language Interface (PLI).
``Synopsys coverage technology has repeatedly proven its value for our projects,'' said Greg Winner, vice president of engineering at AMCC. ``With coverage now built into VCS, our designs teams will be able to easily access coverage metrics within the same Verilog flow, thus allowing us to achieve our quality objectives quickly.''
The VCS DirectC interface significantly improves ease-of-use and performance over existing PLI-based methods by enabling designers to directly embed C/C++ functions within their Verilog design description. VCS automatically recognizes these C/C++ function calls and integrates them into the simulation run, in contrast to interfacing with them via manually created PLI files. Furthermore, using this interface eliminates debugging often associated with PLIs. As a result, VCS DirectC users can expect up to 2x simulation performance improvement over PLI.
``With the VCS DirectC interface, we are able to avoid PLIs, making it easier for us to use C/C++ functions in our system-level verification environment. In addition, we have seen this interface perform faster compared to equivalent PLIs,'' said Masamichi Kawarabayashi, senior engineering manager of NEC Electronics, Inc. ``Using VCS DirectC, we are able to shorten our overall verification cycle.''
``VCS DirectC interface represents a significant improvement in the integration of C/C++ models in a faster Verilog simulation environment. We were able to use VCS DirectC immediately in our memory controller and see its performance benefits,'' said Dave Watson, manager of ASIC development at Agile Storage, Inc. ``We can now focus on the verification effort rather than on developing PLI expertise.''
Complete Functional Verification Solution
VCS(TM) is part of Synopsys' complete line of functional verification solutions supporting Verilog, VHDL, mixed-HDL and mixed-signal simulation for complex SoC designs. These solutions, aimed at achieving the highest verification productivity, include Synopsys' VCS Verilog simulator, Scirocco(TM) VHDL simulator, the MX package for mixed-HDL simulation, CoCentric® System Studio for SystemC simulation, VERA® testbench automation tool, VCS-NanoSim(TM) package for mixed-signal simulation, and Formality® equivalence checker.
Pricing and Availability
VCS 6.0.1 with built-in coverage and DirectC will be available in October 2001. VCS pricing begins at $20,250 for a one-year technology subscription license (TSL). A single license enables VCS to run on any supported platform.
Synopsys, Inc. (Nasdaq:SNPS), headquartered in Mountain View, California, creates leading electronic design automation (EDA) tools for the global electronics market. The company delivers advanced design technologies and solutions to developers of complex integrated circuits, electronic systems and systems on a chip. Synopsys also provides consulting and support services to simplify the overall IC design process and accelerate time to market for its customers. Visit Synopsys at http://www.synopsys.com.
Note to Editors: Synopsys, VERA, CoCentric, and Formality are registered trademarks of Synopsys, Inc. VCS, Scirocco and NanoSim are trademarks of Synopsys. All other trademarks or registered trademarks mentioned in this release are the intellectual property of their respective owners.
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