eMemory's NeoFuse IP Verified in TSMC 10nm FinFET Process
Hsinchu, Taiwan (Nov. 16, 2016) – eMemory, a leading logic NVM IP provider, today announced the successful demonstration of its security-enhanced NeoFuse IP in TSMC’s 10nm FinFET process, along with IP design kits available to customers for product design-in.
Security concerns associated with high-level chips heighten the need for security functions in logic NVM IP with leading-edge process nodes. eMemory’s security-enhanced NeoFuse IP in TSMC’s 10nm FinFET process includes comprehensive security features to prevent attacks such as fault injection, data tampering and side channel attacks. In addition, a voltage tolerance of over 20 percent for read operations enhances design flexibility and reduces power consumption.
The qualification of NeoFuse IP in TSMC’s 16nm FFC process will be done in early 2017, with completion in 10nm FinFET process following in the second half of 2017. eMemory not only delivers a logic NVM solution in TSMC’s leading edge platforms, but has also developed NeoFuse technology for a wide range of other TSMC process technologies such as ULP, CIS, eFlash, HV, and BCD. eMemory’s NeoFuse technology has been developed in 70 process platforms worldwide, 27 of which have already been verified.
Following eMemory’s successful IP development in a variety of TSMC technology nodes over the past 13 years, eMemory continues its close collaboration with TSMC to extend IP availability to multiple process technologies.
About eMemory:
eMemory (Stock Code: 3529) is a global leader in logic process embedded non-volatile memory (eNVM) silicon IP. Since established in 2000, eMemory has been devoted to research and development of innovative technologies, offering the industry’s most comprehensive platforms of patented eNVM IP solutions include NeoBit (OTP Silicon IP), NeoFuse (Anti-Fuse OTP Silicon IP), NeoMTP (1,000+ Times Programmable Silicon IP), NeoFlash (10,000+ Times Programmable Silicon IP), and NeoEE (100,000+ Times Programmable Silicon IP) to semiconductor foundries, integrated devices manufacturers (IDMs) and fabless design houses worldwide. eMemory’s eNVM silicon IPs support a wide range of applications include trimming, function selection, code storage, parameter setting, encryption, and identification setting. The company has the world’s largest NVM engineering team and prides itself on providing partners a full-service solution that sees the integration of eMemory eNVM IP from initial design stages through fabrication. For more information about eMemory, please visit www.ememory.com.tw.
|
Related News
- Synopsys' Custom Compiler Certified for TSMC 10-nm and 7-nm FinFET Process Nodes
- eMemory Announces Industry's First 16nm FinFET Compact (FFC) Process Verified OTP Silicon IP
- TSMC Certifies Synopsys' IC Compiler II on 10-nanometer FinFET Process
- eMemory Announces the First Verified NeoFuse OTP IP in 16nm FinFET Plus Process
- eMemory NeoFuse Technology Is Verified in 16nm FinFET Process
Breaking News
- Arteris Joins Intel Foundry Accelerator Ecosystem Alliance Program to Support Advanced Semiconductor Designs
- SkyeChip Joins Intel Foundry Accelerator IP Alliance
- Siemens and Intel Foundry advance their collaboration to enable cutting-edge integrated circuits and advanced packaging solutions for 2D and 3D IC
- Cadence Expands Design IP Portfolio Optimized for Intel 18A and Intel 18A-P Technologies, Advancing AI, HPC and Mobility Applications
- Synopsys and Intel Foundry Propel Angstrom-Scale Chip Designs on Intel 18A and Intel 18A-P Technologies
Most Popular
- QuickLogic Delivers eFPGA Hard IP for Intel 18A Based Test Chip
- Siemens collaborates with TSMC to drive further innovation in semiconductor design and integration
- Aion Silicon Joins Intel Foundry Accelerator Design Services Alliance to Deliver Next-Generation Custom SoCs at Scale
- TSMC Unveils Next-Generation A14 Process at North America Technology Symposium
- BOS Semiconductors to Partner with Intel to Accelerate Automotive AI Innovation
![]() |
E-mail This Article | ![]() |
![]() |
Printer-Friendly Page |