Enabling the Expanding Cloud: High-Bandwidth Memory and 2.5D Solutions
SAN JOSE, Calif. — November 29, 2016 — eSilicon Corporation, a leading independent semiconductor design and manufacturing solutions provider, was presented the 2016 TSMC OIP Ecosystem Forum Customers’ Choice Award for best paper earlier this month. The paper, Enabling the Expanding Cloud: High-Bandwidth Memory and 2.5D Solutions, was delivered at TSMC’s Open Innovation Platform® Ecosystem Forum on September 22, 2016 in San Jose, CA. The award is based on the popular vote by attendees.
Tom Quan, TSMC director, Open Innovation Platform® Marketing presents the TSMC OIP Customers’ Choice Award to Lisa Minwell, eSilicon senior director, IP Marketing. Minwell presented Enabling the Expanding Cloud: High-Bandwidth Memory and 2.5D Solutions at TSMC’s Open Innovation Platform® Ecosystem Forum on September 22, 2016 in San Jose, CA. The award is based on the popular vote by attendees.
“Adoption of 2.5D requires advanced technology from TSMC, relevant IP and strong design support capability. We’re delighted to be working with eSilicon to enable our mutual customers to access TSMC advanced packaging technology,” said Suk Lee, senior director, Design Infrastructure Marketing Division at TSMC.
“We have a strong pipeline for HBM/2.5 solutions with several customer designs underway right now,” said Lisa Minwell, eSilicon’s senior director, IP marketing. “It’s gratifying to see our technology, design and delivery capability validated by the attendees at the TSMC OIP event.”
eSilicon has been at the forefront of 2.5D/HBM technology for years. Its high-bandwidth memory design (using HBM1) connected devices were first assembled in 2013. eSilicon has been active in the space since then with organic interposer technology, silicon interposer technology, non-interposer-based technologies and the IP needed to enable these technologies — including HBM Gen1 and HBM Gen2 PHY, DLL and I/O libraries from 28nm to 16nm.
eSilicon started the MoZAIC™ program (Modular Z-Axis Integrated Circuit) in 2011, focused on enabling the IP, design capability, packaging, test methodologies and supply chain needed to ensure the lowest-risk, highest-performance device development.
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