SiFive contributes RTL code to community
SAN FRANCISCO – Nov. 29, 2016 – SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of its Freedom Everywhere 310 (FE310) system on a chip (SoC), the industry’s first commercially available SoC based on the free and open RISC-V instruction set architecture, along with the corresponding low-cost HiFive1 software development board. As part of this availability, SiFive also has contributed the register-transfer level (RTL) code for FE310 to the open-source community, which the company revealed today at the 5th RISC-V Workshop in Mountain View, Calif.
“We started with this revolutionary concept — that instruction sets should be free and open – and were amazed by the incredible rippling effect this has had on the semiconductor industry because it provided a viable alternative to what was previously closed and proprietary,” said Krste Asanovic, co-founder and chief architect, SiFive. “In the few short months since we’ve announced the Freedom Platforms, we’ve seen a tremendous response to our vision of customizable SoCs. The FE310 is a major step forward in the movement toward open-source and mass customization, and SiFive is excited to bring the opportunity for innovation back into the hands of system architects.”
The FE310 is the first member of the Freedom Everywhere family of customizable SoCs designed for microcontroller, embedded, IoT and wearable applications. By contributing the FE310 RTL code to the open-source community, SiFive aims to encourage open-source development of both software support for RISC-V as well as other open hardware development. The RTL code also empowers chip designers with the ability to customize their own SoC on top of the base FE310. For system architects, developers or companies without chip design capabilities, SiFive’s “chips-as-a-service” offering can customize the FE310 to meet their unique needs.
“SiFive has achieved a significant milestone for the RISC-V ecosystem,” said Rick O’Connor, executive director of the non-profit RISC-V Foundation. “We are thrilled to see the first commercial silicon based on RISC-V standards come to market and look forward to continued technology leadership from the SiFive team.”
The FE310 features SiFive’s E31 CPU Coreplex, a 32-bit RV32IMAC core running at 320+ MHz. Additional features include a 16KB L1 Instruction Cache, a 16KB Data SRAM scratchpad, hardware multiply/divide, debug module, one-time programmable non-volatile memory (OTP), flexible clock generation with on-chip oscillators and PLLs, and a wide variety of peripherals including UARTs, QSPI, PWMs and timers. Multiple power domains and a low-power standby mode ensure a variety of applications can benefit from the FE310, which was fabricated in TSMC 180nm.
The HiFive1 is an Arduino-Compatible development board featuring the FE310.
The HiFive1 can be ordered via Crowd Supply at https://www.crowdsupply.com/sifive/hifive1. The RTL code for FE310 can be accessed at https://github.com/sifive/freedom.
SiFive is showcasing the HiFive1 at the 5th RISC-V Workshop, in Mountain View Nov. 29-30. The company also will have HiFive1 demos at Booth No. 1522 at ESC Silicon Valley in San Jose from Dec. 6-8.
SiFive is the first fabless provider of customized semiconductors based on the free and open RISC-V instruction set architecture. Founded by RISC-V inventors Krste Asanovic, Yunsup Lee and Andrew Waterman, SiFive democratizes access to custom silicon by helping system designers reduce time-to-market and realize cost savings with customized RISC-V based semiconductors. SiFive is located in San Francisco and has venture backing from Sutter Hill Ventures. For more information, visit www.sifive.com.