14LPP and 28HPC high-bandwidth memory PHY now available
SAN JOSE, Calif. — December 15, 2016 — eSilicon Corporation, a leading independent semiconductor design and manufacturing solutions provider, today announced the availability of its silicon-proven 14nm FinFET and 28nm planar HBM Gen2 Hardened PHY solution.
High-bandwidth memory (HBM), integrated with 2.5D technology, achieves higher bandwidth while using less power in a substantially smaller form factor than DDR4, GDDR5 or hybrid memory cube (HMC).
eSilicon’s HBM Gen2 PHY has been developed to JEDEC JESD235B specification on Samsung 14LPP and TSMC 28HPC technologies. It supports up to 256Gbytes/sec bandwidth with 8x128b channels at 2Gbps per I/O. The integrated I/O supports up to 2Gbps DDR operation across a 4mm interposer channel.
The HBM PHY is DFI 4.0 compliant with several controller-independent features such as:
- READ/WRITE/CK strobe training
- READ leveling training
- I/O calibration
- Lane repair
- Independent programmable control/status registers (CSRs) via APB or IEEE1500 interface
- MISR test
- The PHY may be integrated with any controller
“We are delighted with our complete 2.5D HBM solution,” said Lisa Minwell, eSilicon’s senior director, IP marketing. “eSilicon is delivering a low-risk solution with comprehensive silicon PPA characterization, reliability and test. Our interposer design with full electrical, thermal and mechanical analysis further reduces risk.”
eSilicon has been researching and developing products and processes that deliver a complete 2.5D HBM solution since 2011. eSilicon’s end-to-end HBM solution includes 2.5D ecosystem management, the PHY, ASIC design, SiP design, manufacturing, assembly and test.
Please contact eSilicon at firstname.lastname@example.org for more information, silicon quality results, white papers or data sheets. Or you can download the HBM Gen2 PHY brief.
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