Update: Cadence Completes Acquisition of Tensilica (Apr 24, 2013)
Conexant to Expand on the Benefits of Flexible Length Instructions
Santa Clara, Calif., October 16, 2002 – Tensilica, Inc., the leader in configurable and extensible processors, announced that Bill Huffman, Tensilica's Chief Architect, will preview the next-generation Xtensa processor ISA (instruction set architecture) at the Microprocessor Forum on October 16, 2002 in San Jose, Calif. In this session, Huffman will discuss Tensilica's ideas for a long instruction word format for designer-defined instructions that has many of the benefits of VLIW (performance) but none of the drawbacks (code bloat). Tensilica calls this configurable architecture FLIX for Flexible Length Instruction Xtensions.
Tensilica believes that FLIX will take today's Xtensa processor, which has the industry's highest scores for any embedded processor on the EEMBC (Embedded Microprocessor Benchmark Consortium) benchmarks, to even higher levels of performance by allowing designers to add customized 64-bit instructions that deliver multiple instructions per clock cycle.
As part of the presentation, Moataz Mohamed, Chief Architect, Conexant Systems, Inc. (NASDAQ: CNXT) will describe a new high-performance DSP built using the Xtensa ISA with FLIX. He also will explain why Conexant decided on this joint development/investment project with Tensilica for a very high-performance DSP (digital signal processor). Conexant was planning to develop a high-speed DSP in house for a communications application, but decided instead to work with Tensilica to extend the capabilities of Tensilica's planned architecture.
Add custom 64-bit instructions only where needed
The FLIX capabilities will allow designers to add custom TIE (Tensilica Instruction Extension) language instructions that use longer word lengths to achieve greater parallelism and higher performance. FLIX will allow a modeless mix of 16-, 24-, and 64-bit instructions so code can be fast and parallel when needed or compact when parallelism isn't needed. Using the TIE language, designers can develop an unlimited variety of designer-defined instructions for applications ranging from communications processors to consumer multimedia. The FLIX-enhanced ISA will be fully upwards compatible with all current Xtensa processor configurations.
The FLIX capabilities will be integrated into the comprehensive automated Xtensa processor generator, which automatically generates a complete, correct-by-construction microprocessor, software environment, modeling, and EDA tool support in just over an hour. Any FLIX instructions will immediately and automatically be reflected in the entire software tool chain, significantly reducing design complexity and time-to-market.
The FLIX capabilities set Tensilica's next-generation architecture apart from VLIW (very-long-instruction-word) processors because only those instructions that require the extra bit width use extra bits. VLIW capabilities are notorious for requiring a large increase in code size (code bloat), which doesn't happen with FLIX. Superscalar, out of order, and multi-threading are other techniques that improve performance but cause large increases in gate count for that performance increase. Tensilica believes FLIX is a superior capability because it offers SOC designers a way to manage gate count and performance. FLIX is particularly suited for space-constrained, performance intensive embedded applications.
Tensilica's next-generation FLIX architecture will allow the Xtensa processor to run more than one operation per clock cycle. The more performance per clock cycle, the lower the overall clock frequency and power requirements. Tensilica's Xtensa processor architecture already offers extensible SIMD (single instruction multiple data) capabilities, but very high performance applications require even more parallelism and performance, available with FLIX.
"Tensilica's unique contribution is realizing that only a small subset of instructions need to use very long words," stated Huffman. "By allowing a flexible mix, Tensilica will be able to avoid the code bloat found in most VLIW implementations and develop very efficient processors for a wide variety of embedded applications."
This presentation is a preview of future architectural enhancements and not a product introduction. Tensilica has not yet set a date for product availability.
Tensilica was founded in July 1997 to address the fast-growing market for configurable processors and software development tools for high volume, embedded systems. Using the company's proprietary Xtensa Processor Generator, system-on-chip (SOC) designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours. Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers to achieve optimum application performance in minimum design time. The Company is engaged in research, development, and customer support from its offices in Santa Clara, California; Burlington, Massachusetts; Princeton, NJ; Austin, Texas; Oxford, U.K.; Stockholm, Sweden; Taipei, Taiwan, R.O.C.; and Yokohama, Japan. Tensilica is headquartered in Santa Clara, California (95054) at 3255-6 Scott Boulevard, and can be reached at (408) 986-8000 or via www.tensilica.com on the World Wide Web.
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"Tensilica" and "Xtensa" are registered trademarks belonging to Tensilica Inc. All other trademarks are the property of their respective holders.
Tensilica's announced licensees are Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, Cypress, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes Network Systems, IC4IC, Ikanos Communications, JNI Corporation, Marvell (Galileo Technology), Mindspeed Technologies, National Semiconductor, NEC Networks, NEC Solutions, Nippon Telephone and Telegraph (NTT), Olympus Optical Co. Ltd., ONEX Communications, OptiX Networks, Osaka & Kyoto Universities, TranSwitch Corporation, Trebia Networks, Victor Company of Japan (JVC) and ZiLOG.