Henderson, NV – February 14, 2017 – Aldec, Inc., announced today the latest release of its mixed-language Design Rule Checking (DRC) and Clock Domain Crossing (CDC) verification platform, ALINT-PRO™ 2017.01, a unified framework for static rule-based verification of VHDL and Verilog/SystemVerilog RTL designs targeting FPGAs and ASICs.
“Designers cannot afford to have repetitive RTL coding mistakes slipping through undetected to the very late stages of the design cycle,” said Sergei Zaychenko, Aldec Software Product Manager. “The latest release of ALINT-PRO helps designers and managers ensure a methodical use of design rule checking and CDC verification within a single platform, to uncover hidden bugs and confine non-deterministic defects the same day they were introduced into the design.”
ALINT-PRO 2017.01 Highlights
- Full support for Verilog rule plugins (STARC, DO-254, RMM and Aldec Premium)
- Synthesizing black-box units on-the-fly based on net connections
- CDC Clock/Reset debuggability extensions and improved support of custom synchronizers
- CDC support for Intel Arria, Stratix, Cyclone and MAX libraries
- Editable rule levels and prioritizing violations based on the rule levels
- Directory-based Waivers (to exclude 3rd party blocks entirely)
- Interaction between Violations Viewer and Task Viewer
- Relaxed Restriction rules, no longer blocking the analysis when violated
The latest ALINT-PRO release completely replaces previous Aldec DRC solution, ALINT™, providing a natural verification flow and numerous usability, performance and quality enhancements. Existing users of ALINT are advised to migrate to ALINT-PRO until the end of 2017. The upgrade is free of charge for customers having a valid ALINT maintenance contract. A set of automated migration scripts for projects, preference settings, rule policies and waivers are already built-in into ALINT-PRO. Aldec will provide extensive migration assistance through the Customer Support channel.
ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog and SystemVerilog, which is focused on general issues analysis including: RTL and post-synthesis simulation mismatches, design coding for optimal synthesis, avoiding problems on further design stages, coding for portability and reuse and advanced CDC verification for FPGA and ASIC designs. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically.
The 2017.01 release of ALINT-PRO includes numerous new features, usability enhancements, and performance optimizations. For additional information, tutorials, free evaluation download and What’s New Presentation, visit https://www.aldec.com/Products/ALINT-PRO.
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, Requirements Lifecycle Management, DO-254 Functional Verification, Embedded Solutions and Military/Aerospace solutions.