March 2, 2017 -- ​ The 3D-NoC network-on-chip developed by Leti, STMicroelectronics, and Mentor Graphics under a project coordinated by IRT Nanoelec offers 20% to 40% less energy consumption and higher speeds than other NoCs.
The NoC developed is built on two 28 nm FDSOI stacked circuits, each with 96 processor cores. The cores are integrated on a 65 nm CMOS active interposer layer, which ensures communication between the cores and electrical conversion, reducing the distance between cores to just a few hundred microns. For discrete components on an electronic circuit board, the distance can be several centimeters.
A circuit is currently in fabrication and should be delivered in early 2017. Given the maturity of the technology, it could be transferred to a manufacturer very rapidly.