Leverages SoC interconnect IP RTL to shorten SoC delivery schedules, reduce R&D cost, and optimize power, performance and area
CAMPBELL, Calif. – March 8, 2017 – Arteris Inc., the innovative supplier of silicon-proven commercial system-on-chip (SoC) interconnect IP, today announced its next generation automated interconnect timing solution – the PIANO 2.0 Timing Closure Package. PIANO 2.0 builds on customer silicon experience gathered with FlexNoC Physical™ package to automate interconnect timing closure for both cache coherent and non-coherent subsystems.
With the increased use of smaller geometry semiconductor processes and FinFET transistors, the on-chip interconnect has become a prime source of timing closure issues. These issues are usually found late in the design process which causes schedule slips and delayed time-to-market. Design teams currently deal with these issues by manually inserting pipeline stages in the chip netlist through an engineering change order (ECO) process.
PIANO 2.0 solves back-end timing problems with technology that works earlier in the SoC design flow, thereby reducing schedule risk. Its new technology introduces the concept of physical interconnect distance to customers using Arteris FlexNoC and Ncore interconnect products. First, PIANO calculates the length of individual interconnect links and traces, and then uses information about the semiconductor technology process and performance targets to automatically add interconnect pipelines to close timing. Then PIANO helps validate this timing closure scheme with the physical synthesis capabilities of the Synopsys or Cadence tool chains.
The benefits of PIANO 2.0 include:
- Slashes the time needed to close timing compared to manual pipeline insertion methodologies, which reduces overall schedule risk. With a well-defined methodology, interconnect timing can be closed in as little as 24 hours.
- Shrinks interconnect area by 10-15% compared to manual pipeline insertion methodologies, which over-provision pipeline stages
- Decreases interconnect power consumption due to less pipeline logic and use of fewer low voltage threshold (LVT) cells
- Provides seeding of pipeline stage locations which allows place and route tools a better starting point, eliminating costly place and route cycles
New capabilities in PIANO 2.0:
- Automated interconnect timing closure for both cache coherent and non-coherent interconnect subsystems
- Generation of a meta-floorplan from an IP list to provide timing closure guidance during the SoC architectural development phase
- Input and output of production floorplans in LEF/DEF and TCL formats
- Automatic pipeline insertion with advanced features:
- Edit timing closure parameters to optimize individual timing paths
- Automatically account for crossing between multiple frequency and voltage domains
- Automatically generate timing closure analysis reports
- Integrated with Synopsys’ Design Compiler Graphical and IC Compiler II and Cadence’s Genus and Innovus physical synthesis tool chains.
“The core technology in the PIANO Timing Closure Package was used to tape out several complex FinFET SoC designs on schedule,” said K. Charles Janac, President and CEO of Arteris. “PIANO 2.0 is the result of 18 months of work with leading-edge semiconductor design teams to deliver the next generation automated interconnect timing closure solution that works with both our Ncore cache coherent interconnect and FlexNoC non-coherent interconnect IP products.”
The PIANO 2.0 Timing Closure Package is available immediately as an add-on for FlexNoC and Ncore interconnect IP licensees, with additional features being available in the second quarter of 2017.
Renesas, Horst Rieger, Manager, Design Services at Renesas
“PIANO 2.0 automated closure technology lowers the risks in SoC development schedules that traditionally result from timing closure issues. By applying PIANO 2.0 together with generated placement guides, Renesas was able to close the complex SoC development sooner than we expected,” said Horst Rieger, Manager, Design Services, European Technology Center, Renesas Electronics Europe. “Renesas has been an early user of Arteris’ closure technology, and we plan to continue to use Arteris’ enhanced closure capabilities for our future SoC developments.”
Synopsys, Dr. Antun Domic, Chief Technology Officer
“The FinFET SoC generation poses significant timing closure challenges due to decreased drive strength, longer wire distances, increased relative wire resistance and higher performance requirements,” said Dr. Antun Domic, Chief Technology Officer of Synopsys. “The integration of Arteris’ PIANO 2.0 timing closure solution with our Design Compiler Graphical and IC Compiler II physical tools improves the interconnect timing closure process from early architecture to final place and route. We look forward to working with our mutual customers to automate the SoC interconnect timing closure process.”
The Linley Group, Mike Demler, Senior Analyst
“Closing timing on complex FinFET SoCs is a challenging problem that SoC designers struggle to resolve,” said Mike Demler, Senior Analyst, at The Linley Group. “Arteris’ new PIANO technology is a significant enhancement to the company’s FlexNoC Physical timing closure technology, which automates that process for complex SoC interconnects.”
Arteris, Inc. provides system-on-chip (SoC) interconnect IP and tools to accelerate SoC semiconductor assembly for a wide range of applications. Rapid semiconductor designer adoption by customers such as Samsung, Huawei / HiSilicon, Mobileye, Altera (Intel), and Texas Instruments has resulted in Arteris being the only semiconductor IP company to be ranked in the Inc. 500 and Deloitte Technology Fast 500 lists in 2012 and 2013. Customer results obtained by using the Arteris product line include lower power, higher performance, more efficient design reuse and faster SoC development, leading to lower development and production costs. More information can be found at www.arteris.com.