IRDS points to chip stacks, new architectures
Rick Merritt, EETimes
3/23/2017 05:30 PM EDT
SAN JOSE, Calif. — Traditional semiconductor scaling is expected to reach an end by about 2024, according to a white paper from engineers working on a new version of the semiconductor roadmap. The good news is a wide variety of new kinds of devices, chip stacks and systems innovations promise to continue benefits in computing performance, power and cost.
“Die cost reduction has been enabled so far by concurrent scaling of poly pitch, metal pitch, and cell height scaling. This [will likely] continue until 2024,” according to one of nine white papers published today as part of the International Roadmap for Devices and Systems (IRDS).
Beyond that date “there is no room for contact placement as well as worsening performance as a result of contacted poly pitch (CPP) scaling. It is projected that physical channel length would saturate around 12nm due to worsening electrostatics while CPP would saturate at 24nm to reserve sufficient CD (~11nm) for the device contact providing acceptable parasitics,” the white paper reported.
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