Low-latency architecture paves the way for mass adoption of 100GbE Ethernet
San Jose, Calif. – March 30, 2017 – OmniPHY Inc. today announced silicon availability of its industry-leading, low-latency backplane SerDes PHY which delivers enterprise-class performance in demanding backplane applications. Developed on TSMC’s 28nm process technology based on relevant IEEE 802.3 standards, this solution meets the growing demands of data center applications, while also minimizing latency for emerging applications like financial transaction processing.
“To meet the growing demand for low-latency high-speed Ethernet, we have developed a high-performance design on a mainstream process node,” said Claude Gauthier, Chief Technology Officer of OmniPHY. “Additionally, the design is truly multi-protocol and capable of supporting several protocols from 1- to 28Gb/s. It is great to see the silicon validate our rigorous design methodologies.”
Figure 1: Transmitted 25G Eye Diagram
The industry-standard interfaces offered by OmniPHY are robust and designed to operate under harsh electrical conditions. For additional information on OmniPHY products and solutions, or to schedule a technology demonstration, please contact firstname.lastname@example.org.
Omniphy is an American mixed-signal semiconductor IP company based in San Jose, California, with satellite offices across the world. The company specializes in intellectual property and develops high-performance Ethernet PHYs and SerDes interfaces for the Automotive, Industrial, Consumer, and Networking markets. For more information visit http://omniphysemi.com or contact email@example.com.