JEDEC DDR5 & NVDIMM-P Standards Under Development
Preview both at JEDEC's Server Forum in June 2017
ARLINGTON, Va., USA – MARCH 30, 2017 –JEDEC Solid State Technology Association, the global leader in the development of standards for the microelectronics industry, today announced that development of the widely-anticipated DDR5 (Double Data Rate 5) and NVDIMM-P Design standards is moving forward rapidly. Publication for both is forecasted for 2018. Industry users will have the opportunity to learn more about each standard at JEDEC’s Server Forum event in Santa Clara, CA on Monday, June 19, 2017. For more information and to register, visit the JEDEC website.
JEDEC DDR5 memory will offer improved performance with greater power efficiency as compared to previous generation DRAM technologies. As planned, DDR5 will provide double the bandwidth and density over DDR4, along with delivering improved channel efficiency. These enhancements, combined with a more user-friendly interface for server and client platforms, will enable high performance and improved power management in a wide variety of applications.
As demand for DRAM capacity and bandwidth continues to grow within systems, Hybrid DIMM technologies such as JEDEC NVDIMM-P will enable new memory solutions optimized for cost, power usage and performance. Adding to the existing NVDIMM-N JEDEC standards, NVDIMM-P will be a new high capacity persistent memory module for computing systems.
In addition to the previews at JEDEC’s Server Forum, JEDEC plans to host in-depth technical workshops on both DDR5 and NVDIMM-P to facilitate a better understanding and faster industry-wide adoption of the standards. More details will be available on the JEDEC website later this year.
Mian Quddus, Chairman of the JEDEC Board of Directors, said: “Increasing server performance requirements are driving the need for more advanced technologies, and the standardization of next generation memory such as DDR5 and the new generation persistent modules NVDIMM-P will be essential to fulfilling those needs.” He added, “Work on both standards is progressing quickly, and we invite all interested engineers worldwide to visit the JEDEC website for more information about JEDEC membership and participation in JEDEC standards-setting activities.”
About JEDEC
JEDEC is the global leader in the development of standards for the microelectronics industry. Thousands of volunteers representing nearly 300 member companies work together in 50 JEDEC committees to meet the needs of every segment of the industry, manufacturers and consumers alike. The publications and standards generated by JEDEC committees are accepted throughout the world. All JEDEC standards are available for free download from the JEDEC website. For more information, visit www.jedec.org.
|
Related News
- JEDEC Publishes DDR4 NVDIMM-P Bus Protocol Standard
- Synopsys Announces Industry's First DDR5 NVDIMM-P Verification IP for Next-generation Storage-class Memory Designs
- Design & Reuse's IP Management Enterprise Platform adds IP-centric revision control front end for targeting IP under development
- JEDEC Updates JESD79-5C DDR5 SDRAM Standard: Elevating Performance and Security for Next-Gen Technologies
- Saankhya Labs receives approval under Semiconductor Design Linked Incentive (DLI) scheme for Development of a System-on-Chip (SoC) for 5G Telecom infrastructure equipment
Breaking News
- Rambus Advances AI 2.0 with GDDR7 Memory Controller IP
- Faraday Reports First Quarter 2024 Results
- RAAAM Memory Technologies Closes $4M Seed Round to Commercialize Super Cost Effective On-Chip Memory Solutions
- Alphawave Semi Audited Results for the Year Ended 31 December 2023
- Qualitas Semiconductor Appoints HSRP as its Distributor for the China Markets
Most Popular
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Omni Design Technologies Joins Intel Foundry Accelerator IP Alliance
- Faraday Partners with Arm to Innovate AI-driven Vehicle ASICs
- Semiconductor Capacity Is Up, But Mind the Talent Gap
- Efabless Announces the Release of the OpenLane 2 Development Platform, Transforming Custom Silicon Design Flows
E-mail This Article | Printer-Friendly Page |