April 12, 2017 -- Mentor, a Siemens business, today announced the availability of a qualified reference flow comprising a wide range of design implementation, verification, and test tools and flows optimized for Samsung Electronics’ 14LPP (Low Power Plus) process technology. The announcement includes the Calibre® physical verification suite, Oasys-RTL™ physical synthesis system, Nitro-SoC™ place and route system, and Tessent® test product suite. The reference flow components were validated by Samsung with designs using Samsung’s 14LPP reference process design kits (PDKs), and the ARM CA53 CPU processor as the validation vehicle. The power, performance, area, and design rule checking (DRC) count design objectives for the ARM core were successfully met. By using the Mentor reference flow, Samsung’s 14LPP foundry customers can ensure their designs are released to fabrication in a timely manner, satisfying the strict quality controls and accuracy requirements.
“We worked closely with Mentor to implement a certified reference flow that enables our mutual customers to create innovative designs while achieving first-pass silicon success and reducing time to market,” said Jaehong Park, senior vice president of the Design Service team at Samsung Electronics. “This Mentor reference flow for our 14LPP process technology is an expansion of our long-term partnership that continues to help designers implement, verify, test, and deliver designs with confidence.”
The Oasys-RTL physical RTL synthesis solution was enhanced to support the Samsung 14LPP process for RTL-to-placed-gates flow, including RTL-level floorplanning. The Oasys-RTL tool uses a patented PlaceFirst methodology to integrate placement into the core synthesis algorithm for delivering the best quality of results (QoR) and fastest runtime. Oasys-RTL functionality also includes a unique RTL-level floorplanning technology to automatically generate seed floorplans early in the design cycle.
The Nitro-SoC place and route system was architected to meet the Samsung 14LPP advanced process reference flow requirements for netlist-to-GDSII physical implementation. The Nitro-SoC tool provides a range of innovative technologies, including multi-patterning and FinFET-aware implementation, a flexible routing architecture to encompass all the complex DRC, design for manufacturing (DFM), and multi-patterning rules, a comprehensive multi-VDD-based low power flow, concurrent multi-corner multi-mode (MCMM)-based area optimization, comprehensive parallelization for faster runtimes, easy-to-use built-in reference flows, and native integration with the Calibre sign-off engines.
The industry-leading Calibre platform supplies a number of tools that ensure designers can achieve the verification results they require while minimizing design cycles.
- The Calibre nmDRC™ and Calibre nmLVS™ tools help design teams optimize their designs to meet Samsung 14LPP process requirements, providing innovative and accurate physical and circuit verification that address the complexities of multiple patterning that are inherent with advanced process nodes.
- The Calibre YieldEnhancer tool, via its SmartFill application, is used in the Samsung 14LPP process to control planarity of the design across all intellectual property (IP), blocks, and full chip to ensure consistency on all layers during manufacturing.
- The Calibre xACT™ platform delivers detailed accuracy and high throughput for parasitic extraction, using an integrated field solver to calculate parasitics with attofarad accuracy for complex three-dimensional structures, while optimizing performance for multi-million-instance designs through a highly scalable parallel processing approach.
- Calibre PERC™ reliability software automates complex reliability checks using a pioneering integrated knowledge of both the physical layout and the netlist.
- Calibre Pattern Matching functionality enables a variety of visual geometry analysis, including hotspot identification and verification of precise configuration requirements across multiple instances.
- The Calibre LFD™ tool accurately models the impact of lithographic processes to predict actual “as-manufactured” layout dimensions, identifying any potential lithographic issues and enabling designers to optimize yield and product reliability.
The Tessent product suite is the industry’s most comprehensive design-for-test solution. For manufacturing test applications, Tessent tools provide the industry’s highest test quality, lowest test cost, and fastest time-to-root-cause of test failures. ISO 26262-certified Tessent tools also feature best-in-class in-system test technologies for safety-critical automotive applications.
“Through our collaboration with Samsung, we are delivering a validated reference flow that will enable designers to achieve their sign-off target dates, while ensuring their designs will work as intended,” said Joseph Sawicki, vice president and general manager of the Design-to-Silicon division at Mentor. “Customers using the Mentor reference flow on the Samsung 14LPP process will be able to optimize their designs to best leverage Samsung’s process offering, for initial tapeout and in silicon production.”
About Mentor Graphics
Mentor Graphics Corporation, a Siemens business, is a world leader in electronic hardware and software design solutions, providing products, consulting services, and award-winning support for the world’s most successful electronic, semiconductor, and systems companies. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Web site: http://www.mentor.com.