5nm nanosheet transistors cut power by 75%

June 05, 2017 // By Nick Flaherty, eeNews

Researchers at IBM have developed a practical way to build transistors on a 5nm process that provides a reduction in power consumption of up to 75% or a performance boost of 40% for the same power.

Instead of using FinFET structures, engineers at the IBM-led Research Alliance at the SUNY Polytechnic Institute Colleges of Nanoscale Science and Engineering’s NanoTech Complex in Albany, NY, used a ‘gate-all-around’ (GAA) built with silicon nanosheets. For the last ten years IBM has been working on nanosheets where each 2D layer is one atom thick and stacked layers build up the structure of the transistor.

This enabled the first practical use of extreme UV (EUV) process technology at research partner GLOBAL FOUNDRIES as the nanosheets can be more easily aligned to build up the devices. This provides a 40% performance boost at fixed power over current 10nm FinFET devices, or a 75% power saving for the same performance.

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