TEWKSBURY, MA. -- June 15, 2017 -- Avery Design Systems Inc., an innovator in functional verification productivity solutions, today announced availability of DDR5 Verification IP (VIP) solution targeting the DDR5 ecosystem players including memory, chip set, and IP vendors.
DDR-Xactor VIP supports DDR5 SoC, memory controller, and DFI-PHY designs
- SDRAM memory chip models
- DFI-PHY model
- Memory controller model including initialization, training, and auto sequencing commands
- I2C models
- Timing and protocol checks
- Functional coverage on MRS, RCD, DB register configurations, DDR and LRDIMM address accesses, FSM states, and errors
- DFI and JEDEC protocol analyzer trackers
- Wide range of End2end performance metrics to assess system-level memory bus utilization, latency, and memory controller optimizations
- Models and compliance testsuites are developed 100% in SystemVerilog and UVM.
DDR5 memory models support major approved and draft ballots including, for example
- Speed bin 3200,3600 and 4000
- Burst Length x32
- Connectivity Test
- DDR5 Reset and Initialization sequence
- DDR5 Fast Zero Mode
- CS Training
- Read Training
- Preamble training
- Write Leveling Modes
- Write enable training
- DDR5 Density 8Gb, 16Gb, 32Gb , 64Gb
- Write Pattern Function
- MRS Registers based ballot definitions
- DDR5 ZQ Calibration
- DDR 5 command Truth Table
- Self Refresh power down modes
- All banks/Same Bank Refresh
- Max Power Saving Mode
- Mask Write
Memory models support a full SDRAM/DIMM user API with many advanced features not included in many “free” models such as
- Random data eye DQS timing
- Clock jitter
- CRC/parity error injection
- Backdoor access to DDR chip and DIMM memory locations
- Callbacks and analysis ports for memory access and state transitions
SoC/memory controller verification is performed using the Avery DDR chip/DIMM memory models to test memory controller functions such as memory refresh and control modes such as DDR5’s PDA and modereg readout.
DDR-Xactor supports the JEDEC SDRAM standards including DDR5, DDR4, DDR3, and the JEDEC mobile memory standards including LPDDR4 and LPDDR3, and DRAM module standards for RCD and DB. DDR-Xactor also supports the DFI-PHY 4.0 standards.
“DDR5 memory systems are significantly more challenging to get right than in previous generations. Avery is targeting its early release of DDR5 VIP towards the DDR5 ecosystem including memory, chip set, and IP vendors to promote the comprehensive functional verification and performance tuning”, says Chilai Huang, president of Avery Design Systems.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for RT-level and gate-level X verification; robust core-through-chip-level Verification IP for PCI Express, CCIX, USB, AMBA, UFS, Unipro, CSI-2/DSI-2, Soundwire, Sensewire/I3C, DDR/LPDDR, HBM, HMC, ONFI/Toggle, NVM Express, SAS, SATA, eMMC, SD/SDIO, CAN FD, LIN, FlexRay, HDMI, and DisplayPort standards. The company is a member of the Mentor Graphics Value Added Partnership (VAP) program and has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.