TriCN introduces breakthrough DDR-II SDRAM interface
Next generation interface is backward compatible with original DDR SDRAM product
SAN FRANCISCO, CA –November 4, 2002 –TriCN, a leading developer of intellectual property (IP) for high-speed semiconductor interface technology, today announced the immediate availability of its DDR-II SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) interface. DDR technology currently holds the largest share of the memory market, and the DDR-II SDRAM interface represents the next generation of interfaces designed for this application. The DDR-II SDRAM interface is the latest member of TriCN's family of memory interface products that includes the original DDR SDRAM product, DDR SRAM, DDR FCRAM, and QDR SRAM.
By designing the interface to function in both the SSTL 2.5V and SSTL 1.8V power supply modes, TriCN's DDR-II SDRAM is backward compatible with the original DDR SDRAM interface spec. "As chip designer's transition to the next generation of DDR SDRAM, it is critical that they have backward compatibility," said Ron Nikel, Chief Technology Office of TriCN. "It not only gives them the freedom of choice in the type of memory that they support, but allows them to interface successfully without having to commit precious resources or time to re-engineer previous designs."
Performance Features and Availability
Along with dual power supply modes, TriCN's DDR-II SDRAM interface offers additional flexibility with On Die Termination (ODT) options that are selectable between 75 and 150 Ohms, as well as Differential Strobes. The interface has a maximum operational frequency of 666Mb/s. TriCN's DDR-II SDRAM interface is immediately available for flip chip and bond wire applications in several variations of the TSMC 0.13um process, including 1.0V core supply (low voltage) process.
About TriCN
Founded in 1997, San Francisco, California-based TriCN is a leading developer of high- performance semiconductor interface intellectual property (IP). The company provides a complete portfolio of IP for maximizing data throughput on and off the chip. This IP is designed for IC developers addressing bandwidth-intensive applications, in the communications, networking, data storage, and memory space. TriCN's IP answers these challenges by delivering validated, industry-leading I/O performance and bandwidth density while dramatically streamlining design complexity and time-to-market. TriCN's customers range from startup to established fabless semiconductor and systems companies, including Philips, MIPS Technologies, SGI, IBM, Cognigine, Internet Machines, and Apple Computer.
For more information, please visit TriCN's web site at www.tricn.com.
|
Related News
Breaking News
- Keysight, Synopsys, and Ansys Deliver Radio Frequency Design Migration Flow to TSMC's N6RF+ Process Node
- Siemens collaborates with TSMC on design tool certifications for the foundry's newest processes and other enablement milestones
- Leveraging Cryogenics and Photonics for Quantum Computing
- Kalray Joins Arm Total Design, Extending Collaboration with Arm on Accelerated AI Processing
- Credo at TSMC 2024 North America Technology Symposium
Most Popular
- Huawei Mate 60 Pro processor made on SMIC 7nm N+2 process
- Silicon Creations Reaches Milestone of 10 Million Wafers in Production with TSMC
- GUC provides 3DIC ASIC total service package to AI/HPC/Networking customers
- Analog Bits to Demonstrate Numerous Test Chips Including Portfolio of Power Management and Embedded Clocking and High Accuracy Sensor IP in TSMC N3P Process at TSMC 2024 North America Technology Symposium
- Alphawave Semi: FY 2023 and 2024 YTD Trading Update and Notice of Results
E-mail This Article | Printer-Friendly Page |