Tackles Growing Demands in Performance Standards Required for Framers, Network Processors and Bridge Chips Used on 10G Line Cards for WAN, MAN and SAN Applications
SHEFFIELD, UK – November 01, 2002 - Jennic, a leading supplier of system-level intellectual property (IP) cores and silicon design services, today announced the launch of its second generation SPI-4.2 Physical and Protocol Interface IP cores to address the requirements of next-generation line cards. These fully integrated IP cores are available to semiconductor vendors and system OEMs for incorporation directly into ASSPs or as ASIC/FPGA IP library components.
The Optical Internetworking Forum (OIF), System Packet Interface 4, Phase 2 (SPI-4.2) is rapidly becoming the de-facto standard for providing the interconnect between many of the components, such as the physical layer framers, traffic managers, network processors and switch fabrics found on the OC-192 (10G) line cards used within today's high capacity packet routers.
The next-generation of line-cards will see a rationalisation from the current variety of interfaces in use, such as SPI-4.1, CSIX L1 and OEMs' own proprietary solutions towards SPI-4.2. The standardisation toward SPI-4.2 is driven by the desire of the OEM community to use best-in-class components from a variety of suppliers, rather than go to one supplier for a complete line card solution. Jennic's SPI-4.2 interface enables customers to incorporate its capabilities into their latest designs as well as to upgrade their existing products by replacing their obsolete interfaces. This increases demand for the features and performance of the SPI-4.2 Interface that Jennic has addressed by launching its second-generation product.
"The introduction of our second generation SPI4.2 Interface is in response to the evolving engineering needs in the development of line-cards for Optical and Storage Area Networks", comments Frank Newcombe, Business Development Manager for Optical Networks at Jennic. "Our solutions have been developed in consultation with the leading OEMs and semiconductor suppliers of line-card components to ensure they incorporate the features and performance required for the next generation of applications."
Jennic's SPI4.2 interface contains the physical interface, the protocol manager and data buffer FIFO's to provide a fully integrated, high performance SPI-4.2 interface solution. Designed with multi-port applications in mind, it can support up to 256 channels, making it suitable for channelized SONET and multiplexed Ethernet applications and can sustain SPI-4.2 data rates of up to 16 Gbps. It is available in a number of different configurations and process technologies to address customer's specific architectural requirements. It provides support for the Network Processor Forum, Streaming Interface (NPF SI) and will form the architectural basis of Jennic's forthcoming SPI-5 interface solution. Jennic complements its IP core portfolio by offering digital, mixed signal and SoC design service capabilities to optimize them to customers specific requirements and to implement them into their ASIC/IC products.
The SPI-4.2 Physical Interface provides the physical interface between the internal on-chip bus and the external on-card SPI-4.2 DDR bus running at up to 500MHz. In order to guarantee data integrity in the most demanding applications, such as when the on-card SPI-4.2 bus is providing the interconnect across a backplane, the interface employs Jennic's own LVDS IO cells and a proprietary clock and data alignment mechanism, it supports static and dynamic deskew and uses a high performance PLL to provide a high tolerance to input clock jitter.
"The fully integrated SPI-4.2 Physical and Protocol Interface complement our other system-level IP cores and further illustrate Jennic's abilities in system, digital, mixed signal and SoC engineering", comments Jim Lindop, CEO of Jennic. "Our reputation for offering leading-edge, system-level silicon solutions to tier-one customers will continue with this second generation of SPI-4.2 interface."
By implementing a digital clock and data alignment solution, the interface offers much lower power consumption than traditional analogue solutions and is easier to port between process technologies. The interface is capable of handling data skew of up to ± 1 bit and jitter of 0.44 UI at clock speeds up to 500MHz. The PLL provides a very low jitter clock source (50ps pk-pk), which is used to provide all the system timing functions and provides a low pass filter function which is used to clean up noisy clock input signals, up to 0.10 UI. Facilitating system testing and debugging, the interface provides a variety of diagnostic capabilities, including PRBS pattern generation and checking and loopbacks.
The SPI-4.2 Protocol Interface controls the data transfer across the external SPI-4.2 bus and contains a number of features to maximize the efficiency of transfers, in order to achieve near-maximum theoretical bandwidth utilization of 16 Gbps, and to address the specific requirements of high-end applications. It is available in a number of configurations supporting single or dual or quad port applications and different maximum number of channels (1, 16, 64, 192 and 256).
The multi-port architecture addresses applications such as bridge chips, where the SPI-4.2 interface is being multiplexed between a number of other interfaces. The channelized FIFOs are used to buffer the packet data and perform rate adaptation to minimize packet fragmentation across the SPI-4.2 interface. They can be dynamically reconfigured to allocate capacity on a per channel basis allowing them to adapt to the traffic profile as connections are equipped across the network.
Up to 256 channels are supported for applications such as STS-192 SONET when channelized down to 192 STS-1 channels or the multiplexing of 100 Fast Ethernet connections over 10G Ethernet. A parallel, credit-based arbiter utilizing a fairness algorithm is used to allocate bandwidth to each channel independent of packet size, eliminating some of the problems traditionally associated with a round robin/credit-based arbiter. To minimize the number of inserted idle control words, thereby maximizing bandwidth utilization, the arbiter pre-fetches data from the FIFO for the next data burst. This is particularly important in network processor and traffic managers where the traffic profile can be non-deterministic. Sequence errors and illegal protocol errors are handled in a robust and thorough manner to prevent their propagation to other parts of the system.
The SPI-4.2 IP cores are available now implemented in 0.18µm and 0.13µm CMOS technologies in flip-chip and wire-bond packages. The SPI4.2 Physical Interface is normally provided as a hard macro as its design is technology and package dependant and requires careful layout within tight constraints to ensure correct operation. The SPI-4.2 Protocol Interface is a scaleable design available in a number of configurations supporting different numbers of ports and channels and different sizes of buffer memory. It is largely technology independent but can be optimized to suit RAM availability and ECC requirements. It can be provided as either a hard or soft macro suitable for implementation into either ASIC or FPGA technologies. Jennic also provides design services to tune the IP to customer needs, port to foundries and processes and to provide onwards technical sales and marketing support to the end-customer market.