Cadence Genus Synthesis Solution Enables Toshiba to Complete a Successful ASIC Tapeout with a 2X Logic Synthesis Runtime Improvement

Toshiba also evaluates the Genus physical optimization flow and experiences leakage power reduction

SAN JOSE, Calif. -- Jul 20, 2017 -- Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that Toshiba Electronic Devices & Storage Corporation used the Cadence^® Genus^™ Synthesis Solution to complete a successful ASIC design tapeout. The solution, used with the CPF-based low-power flow, enabled Toshiba to reduce logic synthesis runtime by 2X versus its previous logic synthesis solution. Toshiba also experienced a 5.7 percent leakage power reduction for a standard cell portion during a trial evaluation of the Genus Synthesis Solution’s physical optimization flow, which reduced low Vth cell usage while maintaining timing and area.

For more information on the Genus Synthesis Solution, please visit www.cadence.com/go/genus.

The Genus Synthesis Solution enabled the Toshiba team to improve productivity during register-transfer-level (RTL) synthesis and to optimize power, performance and area (PPA) in the final implementation. The solution’s massively parallel architecture provided Toshiba with timing-driven distributed synthesis of the design across multiple CPUs. Furthermore, Toshiba’s use of the Genus Synthesis Solution’s physical optimization flow improves silicon accuracy by modeling physical wiring effects from the earliest stages of the synthesis process, resulting in better design PPA.

“We work daily to create design development methodologies that ensure our products meet or exceed customer and internal product planning team requirements for quality and reduced time to market,” said Atsuyuki Okumura, chief specialist, Design Technology Development Department, Center for Semiconductor Research & Development at Toshiba Electronic Devices & Storage Corporation. “To speed time to market, it is important that we shorten the runtime of logic synthesis tools. With the Genus Synthesis Solution, we reduced the logic synthesis runtime with the delivery of our ASIC design while obtaining equivalent Quality of Results (QoR) when compared with our previous RTL compiler solution. We’ve also achieved successful results during our evaluation of the Genus physical optimization flow for leakage power reduction and are continuing to evaluate this flow.”

The Genus Synthesis Solution is a next-generation RTL synthesis and physical synthesis engine that addresses the productivity challenges faced by RTL designers. It is a part of the Cadence digital design platform that supports the company’s overall System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently.

About Cadence

Cadence enables electronic systems and semiconductor companies to create the innovative end products that are transforming the way people live, work and play. Cadence^® software, hardware and semiconductor IP are used by customers to deliver products to market faster. The company’s System Design Enablement strategy helps customers develop differentiated products—from chips to boards to systems—in mobile, consumer, cloud datacenter, automotive, aerospace, IoT, industrial and other market segments. Cadence is listed as one of Fortune Magazine's 100 Best Companies to Work For. Learn more at www.cadence.com.

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