Chiplets seen as the future of IP blocks
Rick Merritt, EETimes, Aug. 23, 2017 –
CUPERTINO, Calif. - A U.S. research effort aims to nurture an ecosystem for designing semiconductors from plug-and-play chiplets. It arrives at a time when rivals such as Intel and Xilinx are using proprietary packaging techniques to differentiate competing FPGAs.
Over the next eight months, the Common Heterogeneous Integration and IP Reuse Strategies (CHIPS) program under the Defense Advanced Research Projects Agency aims to define and test open chip interfaces. Within three years it hopes multiple companies will use the links to connect a wide range of die to form sophisticated components.
Intel has signed up for the program, and others are expected to follow soon. Internally, the x86 giant is debating whether to open up parts of its embedded multi-die interconnect bridge (EMIB) as part of its participation. The company gave the most detailed look at EMIB to date at the Hot Chips event here.